1 | /********************************************************************* |
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2 | Blosc - Blocked Shuffling and Compression Library |
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3 | |
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4 | Author: Francesc Alted <[email protected]> |
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5 | Creation date: 2009-05-20 |
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6 | |
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7 | See LICENSES/BLOSC.txt for details about copyright and rights to use. |
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8 | **********************************************************************/ |
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9 | |
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10 | #include "shuffle.h" |
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11 | #include "shuffle-common.h" |
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12 | #include "shuffle-generic.h" |
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13 | #include "bitshuffle-generic.h" |
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14 | #include <stdio.h> |
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15 | #include <string.h> |
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16 | |
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17 | /* Visual Studio < 2013 does not have stdbool.h so here it is a replacement: */ |
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18 | #if defined __STDC__ && defined __STDC_VERSION__ && __STDC_VERSION__ >= 199901L |
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19 | /* have a C99 compiler */ |
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20 | typedef _Bool bool; |
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21 | #else |
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22 | /* do not have a C99 compiler */ |
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23 | typedef unsigned char bool; |
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24 | #endif |
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25 | static const bool false = 0; |
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26 | static const bool true = 1; |
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27 | |
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28 | |
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29 | #if !defined(__clang__) && defined(__GNUC__) && defined(__GNUC_MINOR__) && \ |
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30 | __GNUC__ >= 5 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) |
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31 | #define HAVE_CPU_FEAT_INTRIN |
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32 | #endif |
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33 | |
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34 | /* Include hardware-accelerated shuffle/unshuffle routines based on |
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35 | the target architecture. Note that a target architecture may support |
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36 | more than one type of acceleration!*/ |
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37 | #if defined(SHUFFLE_AVX2_ENABLED) |
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38 | #include "shuffle-avx2.h" |
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39 | #include "bitshuffle-avx2.h" |
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40 | #endif /* defined(SHUFFLE_AVX2_ENABLED) */ |
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41 | |
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42 | #if defined(SHUFFLE_SSE2_ENABLED) |
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43 | #include "shuffle-sse2.h" |
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44 | #include "bitshuffle-sse2.h" |
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45 | #endif /* defined(SHUFFLE_SSE2_ENABLED) */ |
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46 | |
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47 | |
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48 | /* Define function pointer types for shuffle/unshuffle routines. */ |
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49 | typedef void(*shuffle_func)(const size_t, const size_t, const uint8_t*, const uint8_t*); |
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50 | typedef void(*unshuffle_func)(const size_t, const size_t, const uint8_t*, const uint8_t*); |
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51 | typedef int64_t(*bitshuffle_func)(void*, void*, const size_t, const size_t, void*); |
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52 | typedef int64_t(*bitunshuffle_func)(void*, void*, const size_t, const size_t, void*); |
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53 | |
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54 | /* An implementation of shuffle/unshuffle routines. */ |
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55 | typedef struct shuffle_implementation { |
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56 | /* Name of this implementation. */ |
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57 | const char* name; |
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58 | /* Function pointer to the shuffle routine for this implementation. */ |
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59 | shuffle_func shuffle; |
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60 | /* Function pointer to the unshuffle routine for this implementation. */ |
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61 | unshuffle_func unshuffle; |
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62 | /* Function pointer to the bitshuffle routine for this implementation. */ |
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63 | bitshuffle_func bitshuffle; |
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64 | /* Function pointer to the bitunshuffle routine for this implementation. */ |
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65 | bitunshuffle_func bitunshuffle; |
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66 | } shuffle_implementation_t; |
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67 | |
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68 | typedef enum { |
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69 | BLOSC_HAVE_NOTHING = 0, |
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70 | BLOSC_HAVE_SSE2 = 1, |
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71 | BLOSC_HAVE_AVX2 = 2 |
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72 | } blosc_cpu_features; |
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73 | |
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74 | /* Detect hardware and set function pointers to the best shuffle/unshuffle |
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75 | implementations supported by the host processor. */ |
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76 | #if defined(SHUFFLE_AVX2_ENABLED) || defined(SHUFFLE_SSE2_ENABLED) /* Intel/i686 */ |
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77 | |
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78 | /* Disabled the __builtin_cpu_supports() call, as it has issues with |
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79 | new versions of gcc (like 5.3.1 in forthcoming ubuntu/xenial: |
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80 | "undefined symbol: __cpu_model" |
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81 | For a similar report, see: |
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82 | https://lists.fedoraproject.org/archives/list/[email protected]/thread/ZM2L65WIZEEQHHLFERZYD5FAG7QY2OGB/ |
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83 | */ |
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84 | #if defined(HAVE_CPU_FEAT_INTRIN) && 0 |
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85 | static blosc_cpu_features blosc_get_cpu_features(void) { |
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86 | blosc_cpu_features cpu_features = BLOSC_HAVE_NOTHING; |
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87 | if (__builtin_cpu_supports("sse2")) { |
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88 | cpu_features |= BLOSC_HAVE_SSE2; |
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89 | } |
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90 | if (__builtin_cpu_supports("avx2")) { |
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91 | cpu_features |= BLOSC_HAVE_AVX2; |
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92 | } |
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93 | return cpu_features; |
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94 | } |
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95 | #else |
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96 | |
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97 | #if defined(_MSC_VER) && !defined(__clang__) |
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98 | #include <intrin.h> /* Needed for __cpuid */ |
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99 | |
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100 | /* _xgetbv is only supported by VS2010 SP1 and newer versions of VS. */ |
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101 | #if _MSC_FULL_VER >= 160040219 |
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102 | #include <immintrin.h> /* Needed for _xgetbv */ |
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103 | #elif defined(_M_IX86) |
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104 | |
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105 | /* Implement _xgetbv for VS2008 and VS2010 RTM with 32-bit (x86) targets. */ |
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106 | |
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107 | static uint64_t _xgetbv(uint32_t xcr) { |
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108 | uint32_t xcr0, xcr1; |
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109 | __asm { |
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110 | mov ecx, xcr |
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111 | _asm _emit 0x0f _asm _emit 0x01 _asm _emit 0xd0 |
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112 | mov xcr0, eax |
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113 | mov xcr1, edx |
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114 | } |
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115 | return ((uint64_t)xcr1 << 32) | xcr0; |
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116 | } |
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117 | |
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118 | #elif defined(_M_X64) |
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119 | |
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120 | /* Implement _xgetbv for VS2008 and VS2010 RTM with 64-bit (x64) targets. |
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121 | These compilers don't support any of the newer acceleration ISAs |
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122 | (e.g., AVX2) supported by blosc, and all x64 hardware supports SSE2 |
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123 | which means we can get away with returning a hard-coded value from |
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124 | this implementation of _xgetbv. */ |
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125 | |
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126 | static inline uint64_t |
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127 | _xgetbv(uint32_t xcr) { |
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128 | /* A 64-bit OS must have XMM save support. */ |
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129 | return xcr == 0 ? (1UL << 1) : 0UL; |
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130 | } |
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131 | |
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132 | #else |
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133 | |
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134 | /* Hardware detection for any other MSVC targets (e.g., ARM) |
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135 | isn't implemented at this time. */ |
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136 | #error This version of c-blosc only supports x86 and x64 targets with MSVC. |
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137 | |
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138 | #endif /* _MSC_FULL_VER >= 160040219 */ |
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139 | |
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140 | #else |
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141 | |
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142 | /* Implement the __cpuid and __cpuidex intrinsics for GCC, Clang, |
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143 | and others using inline assembly. */ |
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144 | __attribute__((always_inline)) |
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145 | static inline void |
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146 | __cpuidex(int32_t cpuInfo[4], int32_t function_id, int32_t subfunction_id) { |
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147 | __asm__ __volatile__ ( |
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148 | # if defined(__i386__) && defined (__PIC__) |
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149 | /* Can't clobber ebx with PIC running under 32-bit, so it needs to be manually restored. |
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150 | https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family |
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151 | */ |
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152 | "movl %%ebx, %%edi\n\t" |
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153 | "cpuid\n\t" |
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154 | "xchgl %%ebx, %%edi": |
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155 | "=D" (cpuInfo[1]), |
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156 | #else |
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157 | "cpuid": |
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158 | "=b" (cpuInfo[1]), |
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159 | #endif /* defined(__i386) && defined(__PIC__) */ |
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160 | "=a" (cpuInfo[0]), |
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161 | "=c" (cpuInfo[2]), |
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162 | "=d" (cpuInfo[3]) : |
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163 | "a" (function_id), "c" (subfunction_id) |
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164 | ); |
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165 | } |
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166 | |
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167 | #define __cpuid(cpuInfo, function_id) __cpuidex(cpuInfo, function_id, 0) |
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168 | |
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169 | #define _XCR_XFEATURE_ENABLED_MASK 0 |
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170 | |
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171 | /* Reads the content of an extended control register. |
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172 | https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family |
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173 | */ |
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174 | static inline uint64_t |
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175 | _xgetbv(uint32_t xcr) { |
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176 | uint32_t eax, edx; |
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177 | __asm__ __volatile__ ( |
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178 | /* "xgetbv" |
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179 | This is specified as raw instruction bytes due to some older compilers |
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180 | having issues with the mnemonic form. |
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181 | */ |
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182 | ".byte 0x0f, 0x01, 0xd0": |
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183 | "=a" (eax), |
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184 | "=d" (edx) : |
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185 | "c" (xcr) |
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186 | ); |
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187 | return ((uint64_t)edx << 32) | eax; |
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188 | } |
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189 | |
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190 | #endif /* defined(_MSC_FULL_VER) */ |
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191 | |
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192 | #ifndef _XCR_XFEATURE_ENABLED_MASK |
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193 | #define _XCR_XFEATURE_ENABLED_MASK 0x0 |
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194 | #endif |
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195 | |
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196 | static blosc_cpu_features blosc_get_cpu_features(void) { |
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197 | blosc_cpu_features result = BLOSC_HAVE_NOTHING; |
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198 | int32_t max_basic_function_id; |
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199 | /* Holds the values of eax, ebx, ecx, edx set by the `cpuid` instruction */ |
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200 | int32_t cpu_info[4]; |
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201 | int sse2_available; |
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202 | int sse3_available; |
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203 | int ssse3_available; |
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204 | int sse41_available; |
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205 | int sse42_available; |
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206 | int xsave_available; |
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207 | int xsave_enabled_by_os; |
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208 | int avx2_available = 0; |
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209 | int avx512bw_available = 0; |
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210 | int xmm_state_enabled = 0; |
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211 | int ymm_state_enabled = 0; |
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212 | int zmm_state_enabled = 0; |
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213 | uint64_t xcr0_contents; |
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214 | |
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215 | /* Get the number of basic functions available. */ |
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216 | __cpuid(cpu_info, 0); |
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217 | max_basic_function_id = cpu_info[0]; |
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218 | |
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219 | /* Check for SSE-based features and required OS support */ |
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220 | __cpuid(cpu_info, 1); |
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221 | sse2_available = (cpu_info[3] & (1 << 26)) != 0; |
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222 | sse3_available = (cpu_info[2] & (1 << 0)) != 0; |
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223 | ssse3_available = (cpu_info[2] & (1 << 9)) != 0; |
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224 | sse41_available = (cpu_info[2] & (1 << 19)) != 0; |
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225 | sse42_available = (cpu_info[2] & (1 << 20)) != 0; |
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226 | |
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227 | xsave_available = (cpu_info[2] & (1 << 26)) != 0; |
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228 | xsave_enabled_by_os = (cpu_info[2] & (1 << 27)) != 0; |
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229 | |
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230 | /* Check for AVX-based features, if the processor supports extended features. */ |
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231 | if (max_basic_function_id >= 7) { |
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232 | __cpuid(cpu_info, 7); |
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233 | avx2_available = (cpu_info[1] & (1 << 5)) != 0; |
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234 | avx512bw_available = (cpu_info[1] & (1 << 30)) != 0; |
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235 | } |
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236 | |
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237 | /* Even if certain features are supported by the CPU, they may not be supported |
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238 | by the OS (in which case using them would crash the process or system). |
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239 | If xsave is available and enabled by the OS, check the contents of the |
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240 | extended control register XCR0 to see if the CPU features are enabled. */ |
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241 | #if defined(_XCR_XFEATURE_ENABLED_MASK) |
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242 | if (xsave_available && xsave_enabled_by_os && ( |
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243 | sse2_available || sse3_available || ssse3_available |
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244 | || sse41_available || sse42_available |
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245 | || avx2_available || avx512bw_available)) { |
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246 | /* Determine which register states can be restored by the OS. */ |
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247 | xcr0_contents = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); |
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248 | |
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249 | xmm_state_enabled = (xcr0_contents & (1UL << 1)) != 0; |
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250 | ymm_state_enabled = (xcr0_contents & (1UL << 2)) != 0; |
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251 | |
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252 | /* Require support for both the upper 256-bits of zmm0-zmm15 to be |
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253 | restored as well as all of zmm16-zmm31 and the opmask registers. */ |
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254 | zmm_state_enabled = (xcr0_contents & 0x70) == 0x70; |
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255 | } |
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256 | #endif /* defined(_XCR_XFEATURE_ENABLED_MASK) */ |
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257 | |
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258 | #if defined(BLOSC_DUMP_CPU_INFO) |
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259 | printf("Shuffle CPU Information:\n"); |
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260 | printf("SSE2 available: %s\n", sse2_available ? "True" : "False"); |
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261 | printf("SSE3 available: %s\n", sse3_available ? "True" : "False"); |
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262 | printf("SSSE3 available: %s\n", ssse3_available ? "True" : "False"); |
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263 | printf("SSE4.1 available: %s\n", sse41_available ? "True" : "False"); |
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264 | printf("SSE4.2 available: %s\n", sse42_available ? "True" : "False"); |
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265 | printf("AVX2 available: %s\n", avx2_available ? "True" : "False"); |
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266 | printf("AVX512BW available: %s\n", avx512bw_available ? "True" : "False"); |
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267 | printf("XSAVE available: %s\n", xsave_available ? "True" : "False"); |
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268 | printf("XSAVE enabled: %s\n", xsave_enabled_by_os ? "True" : "False"); |
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269 | printf("XMM state enabled: %s\n", xmm_state_enabled ? "True" : "False"); |
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270 | printf("YMM state enabled: %s\n", ymm_state_enabled ? "True" : "False"); |
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271 | printf("ZMM state enabled: %s\n", zmm_state_enabled ? "True" : "False"); |
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272 | #endif /* defined(BLOSC_DUMP_CPU_INFO) */ |
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273 | |
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274 | /* Using the gathered CPU information, determine which implementation to use. */ |
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275 | /* technically could fail on sse2 cpu on os without xmm support, but that |
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276 | * shouldn't exist anymore */ |
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277 | if (sse2_available) { |
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278 | result |= BLOSC_HAVE_SSE2; |
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279 | } |
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280 | if (xmm_state_enabled && ymm_state_enabled && avx2_available) { |
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281 | result |= BLOSC_HAVE_AVX2; |
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282 | } |
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283 | return result; |
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284 | } |
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285 | #endif |
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286 | |
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287 | #else /* No hardware acceleration supported for the target architecture. */ |
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288 | #if defined(_MSC_VER) |
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289 | #pragma message("Hardware-acceleration detection not implemented for the target architecture. Only the generic shuffle/unshuffle routines will be available.") |
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290 | #else |
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291 | #warning Hardware-acceleration detection not implemented for the target architecture. Only the generic shuffle/unshuffle routines will be available. |
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292 | #endif |
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293 | |
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294 | static blosc_cpu_features blosc_get_cpu_features(void) { |
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295 | return BLOSC_HAVE_NOTHING; |
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296 | } |
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297 | |
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298 | #endif |
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299 | |
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300 | static shuffle_implementation_t get_shuffle_implementation() { |
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301 | blosc_cpu_features cpu_features = blosc_get_cpu_features(); |
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302 | shuffle_implementation_t impl_generic; |
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303 | |
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304 | #if defined(SHUFFLE_AVX2_ENABLED) |
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305 | if (cpu_features & BLOSC_HAVE_AVX2) { |
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306 | shuffle_implementation_t impl_avx2; |
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307 | impl_avx2.name = "avx2"; |
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308 | impl_avx2.shuffle = (shuffle_func)shuffle_avx2; |
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309 | impl_avx2.unshuffle = (unshuffle_func)unshuffle_avx2; |
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310 | impl_avx2.bitshuffle = (bitshuffle_func)bshuf_trans_bit_elem_avx2; |
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311 | impl_avx2.bitunshuffle = (bitunshuffle_func)bshuf_untrans_bit_elem_avx2; |
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312 | return impl_avx2; |
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313 | } |
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314 | #endif /* defined(SHUFFLE_AVX2_ENABLED) */ |
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315 | |
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316 | #if defined(SHUFFLE_SSE2_ENABLED) |
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317 | if (cpu_features & BLOSC_HAVE_SSE2) { |
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318 | shuffle_implementation_t impl_sse2; |
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319 | impl_sse2.name = "sse2"; |
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320 | impl_sse2.shuffle = (shuffle_func)shuffle_sse2; |
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321 | impl_sse2.unshuffle = (unshuffle_func)unshuffle_sse2; |
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322 | impl_sse2.bitshuffle = (bitshuffle_func)bshuf_trans_bit_elem_sse2; |
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323 | impl_sse2.bitunshuffle = (bitunshuffle_func)bshuf_untrans_bit_elem_sse2; |
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324 | return impl_sse2; |
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325 | } |
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326 | #endif /* defined(SHUFFLE_SSE2_ENABLED) */ |
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327 | |
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328 | /* Processor doesn't support any of the hardware-accelerated implementations, |
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329 | so use the generic implementation. */ |
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330 | impl_generic.name = "generic"; |
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331 | impl_generic.shuffle = (shuffle_func)shuffle_generic; |
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332 | impl_generic.unshuffle = (unshuffle_func)unshuffle_generic; |
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333 | impl_generic.bitshuffle = (bitshuffle_func)bshuf_trans_bit_elem_scal; |
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334 | impl_generic.bitunshuffle = (bitunshuffle_func)bshuf_untrans_bit_elem_scal; |
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335 | return impl_generic; |
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336 | } |
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337 | |
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338 | |
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339 | /* Flag indicating whether the implementation has been initialized. |
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340 | Zero means it hasn't been initialized, non-zero means it has. */ |
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341 | static int32_t implementation_initialized; |
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342 | |
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343 | /* The dynamically-chosen shuffle/unshuffle implementation. |
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344 | This is only safe to use once `implementation_initialized` is set. */ |
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345 | static shuffle_implementation_t host_implementation; |
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346 | |
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347 | /* Initialize the shuffle implementation, if necessary. */ |
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348 | #if defined(__GNUC__) || defined(__clang__) |
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349 | __attribute__((always_inline)) |
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350 | #endif |
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351 | static |
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352 | #if defined(_MSC_VER) |
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353 | __forceinline |
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354 | #else |
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355 | inline |
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356 | #endif |
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357 | void init_shuffle_implementation() { |
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358 | /* Initialization could (in rare cases) take place concurrently on |
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359 | multiple threads, but it shouldn't matter because the |
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360 | initialization should return the same result on each thread (so |
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361 | the implementation will be the same). Since that's the case we |
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362 | can avoid complicated synchronization here and get a small |
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363 | performance benefit because we don't need to perform a volatile |
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364 | load on the initialization variable each time this function is |
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365 | called. */ |
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366 | #if defined(__GNUC__) || defined(__clang__) |
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367 | if (__builtin_expect(!implementation_initialized, 0)) { |
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368 | #else |
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369 | if (!implementation_initialized) { |
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370 | #endif |
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371 | /* Initialize the implementation. */ |
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372 | host_implementation = get_shuffle_implementation(); |
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373 | |
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374 | /* Set the flag indicating the implementation has been initialized. */ |
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375 | implementation_initialized = 1; |
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376 | } |
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377 | } |
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378 | |
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379 | /* Shuffle a block by dynamically dispatching to the appropriate |
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380 | hardware-accelerated routine at run-time. */ |
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381 | void |
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382 | shuffle(const size_t bytesoftype, const size_t blocksize, |
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383 | const uint8_t* _src, const uint8_t* _dest) { |
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384 | /* Initialize the shuffle implementation if necessary. */ |
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385 | init_shuffle_implementation(); |
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386 | |
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387 | /* The implementation is initialized. |
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388 | Dispatch to it's shuffle routine. */ |
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389 | (host_implementation.shuffle)(bytesoftype, blocksize, _src, _dest); |
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390 | } |
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391 | |
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392 | /* Unshuffle a block by dynamically dispatching to the appropriate |
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393 | hardware-accelerated routine at run-time. */ |
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394 | void |
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395 | unshuffle(const size_t bytesoftype, const size_t blocksize, |
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396 | const uint8_t* _src, const uint8_t* _dest) { |
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397 | /* Initialize the shuffle implementation if necessary. */ |
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398 | init_shuffle_implementation(); |
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399 | |
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400 | /* The implementation is initialized. |
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401 | Dispatch to it's unshuffle routine. */ |
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402 | (host_implementation.unshuffle)(bytesoftype, blocksize, _src, _dest); |
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403 | } |
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404 | |
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405 | /* Bit-shuffle a block by dynamically dispatching to the appropriate |
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406 | hardware-accelerated routine at run-time. */ |
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407 | int |
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408 | bitshuffle(const size_t bytesoftype, const size_t blocksize, |
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409 | const uint8_t* const _src, const uint8_t* _dest, |
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410 | const uint8_t* _tmp) { |
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411 | int size = blocksize / bytesoftype; |
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412 | /* Initialize the shuffle implementation if necessary. */ |
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413 | init_shuffle_implementation(); |
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414 | |
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415 | if ((size % 8) == 0) |
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416 | /* The number of elems is a multiple of 8 which is supported by |
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417 | bitshuffle. */ |
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418 | return (int)(host_implementation.bitshuffle)((void*)_src, (void*)_dest, |
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419 | blocksize / bytesoftype, |
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420 | bytesoftype, (void*)_tmp); |
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421 | else |
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422 | memcpy((void*)_dest, (void*)_src, blocksize); |
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423 | return size; |
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424 | } |
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425 | |
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426 | /* Bit-unshuffle a block by dynamically dispatching to the appropriate |
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427 | hardware-accelerated routine at run-time. */ |
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428 | int |
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429 | bitunshuffle(const size_t bytesoftype, const size_t blocksize, |
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430 | const uint8_t* const _src, const uint8_t* _dest, |
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431 | const uint8_t* _tmp) { |
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432 | int size = blocksize / bytesoftype; |
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433 | /* Initialize the shuffle implementation if necessary. */ |
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434 | init_shuffle_implementation(); |
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435 | |
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436 | if ((size % 8) == 0) |
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437 | /* The number of elems is a multiple of 8 which is supported by |
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438 | bitshuffle. */ |
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439 | return (int)(host_implementation.bitunshuffle)((void*)_src, (void*)_dest, |
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440 | blocksize / bytesoftype, |
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441 | bytesoftype, (void*)_tmp); |
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442 | else |
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443 | memcpy((void*)_dest, (void*)_src, blocksize); |
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444 | return size; |
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445 | } |
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