WikiStart: llvm_bgq_r157929-20120602.patch

File llvm_bgq_r157929-20120602.patch, 171.7 KB (added by hfinkel, 5 years ago)
  • include/llvm/IntrinsicsPowerPC.td

    diff --git a/include/llvm/IntrinsicsPowerPC.td b/include/llvm/IntrinsicsPowerPC.td
    index da85bfb..de0acfb 100644
    a b  
    463463def int_ppc_altivec_vlogefp   : PowerPC_Vec_FF_Intrinsic<"vlogefp">; 
    464464def int_ppc_altivec_vrefp     : PowerPC_Vec_FF_Intrinsic<"vrefp">; 
    465465def int_ppc_altivec_vrsqrtefp : PowerPC_Vec_FF_Intrinsic<"vrsqrtefp">; 
     466 
     467//===----------------------------------------------------------------------===// 
     468// PowerPC FP2 (Double Hummer) Intrinsics. 
     469// 
     470 
     471let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.". 
     472  /// PowerPC_FP2_Intrinsic - Base class for all FP2 intrinsics. 
     473  class PowerPC_FP2_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types, 
     474                              list<LLVMType> param_types, 
     475                              list<IntrinsicProperty> properties> 
     476    : GCCBuiltin<!strconcat("__builtin_fp2_", GCCIntSuffix)>, 
     477      Intrinsic<ret_types, param_types, properties>; 
     478} 
     479 
     480//===----------------------------------------------------------------------===// 
     481// PowerPC Double Hummer Intrinsic Class Definitions. 
     482// 
     483 
     484/// PowerPC_FP2_FF_Intrinsic - A PowerPC intrinsic that takes one v2f64 
     485/// vector and returns one.  These intrinsics have no side effects. 
     486class PowerPC_FP2_FF_Intrinsic<string GCCIntSuffix> 
     487  : PowerPC_FP2_Intrinsic<GCCIntSuffix, 
     488                          [llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; 
     489 
     490/// PowerPC_FP2_FFF_Intrinsic - A PowerPC intrinsic that takes two v2f64 
     491/// vectors and returns one.  These intrinsics have no side effects. 
     492class PowerPC_FP2_FFF_Intrinsic<string GCCIntSuffix> 
     493  : PowerPC_FP2_Intrinsic<GCCIntSuffix, 
     494                          [llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], 
     495                          [IntrNoMem]>; 
     496 
     497/// PowerPC_FP2_FFFF_Intrinsic - A PowerPC intrinsic that takes three v2f64 
     498/// vectors and returns one.  These intrinsics have no side effects. 
     499class PowerPC_FP2_FFFF_Intrinsic<string GCCIntSuffix> 
     500  : PowerPC_FP2_Intrinsic<GCCIntSuffix, 
     501                          [llvm_v2f64_ty], 
     502                          [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], 
     503                          [IntrNoMem]>; 
     504 
     505/// PowerPC_FP2_Load_Intrinsic - A PowerPC intrinsic that takes a pointer 
     506/// and returns a v2f64. 
     507class PowerPC_FP2_Load_Intrinsic<string GCCIntSuffix> 
     508  : PowerPC_FP2_Intrinsic<GCCIntSuffix, 
     509                          [llvm_v2f64_ty], [llvm_ptr_ty], [IntrReadMem]>; 
     510 
     511/// PowerPC_FP2_Store_Intrinsic - A PowerPC intrinsic that takes a pointer 
     512/// and stores a v2f64. 
     513class PowerPC_FP2_Store_Intrinsic<string GCCIntSuffix> 
     514  : PowerPC_FP2_Intrinsic<GCCIntSuffix, 
     515                          [], [llvm_v2f64_ty, llvm_ptr_ty], []>; 
     516 
     517//===----------------------------------------------------------------------===// 
     518// PowerPC Double Hummer Intrinsic Definitions. 
     519 
     520let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.". 
     521  // Add Instructions 
     522  def int_ppc_fp2_fpadd : PowerPC_FP2_FFF_Intrinsic<"fpadd">; 
     523  def int_ppc_fp2_fpsub : PowerPC_FP2_FFF_Intrinsic<"fpsub">; 
     524   
     525  // Estimate Instructions 
     526  def int_ppc_fp2_fpre : PowerPC_FP2_FF_Intrinsic<"fpre">; 
     527  def int_ppc_fp2_fprsqrte : PowerPC_FP2_FF_Intrinsic<"fprsqrte">; 
     528   
     529  // Multiply Instructions 
     530  def int_ppc_fp2_fpmul : PowerPC_FP2_FFF_Intrinsic<"fpmul">; 
     531  def int_ppc_fp2_fxmul : PowerPC_FP2_FFF_Intrinsic<"fxmul">; 
     532  def int_ppc_fp2_fxpmul : PowerPC_FP2_FFF_Intrinsic<"fxpmul">; 
     533  def int_ppc_fp2_fxsmul : PowerPC_FP2_FFF_Intrinsic<"fxsmul">; 
     534   
     535  // Multiply-add instructions 
     536  def int_ppc_fp2_fpmadd : PowerPC_FP2_FFFF_Intrinsic<"fpmadd">; 
     537  def int_ppc_fp2_fpnmadd : PowerPC_FP2_FFFF_Intrinsic<"fpnmadd">; 
     538  def int_ppc_fp2_fpmsub : PowerPC_FP2_FFFF_Intrinsic<"fpmsub">; 
     539  def int_ppc_fp2_fpnmsub : PowerPC_FP2_FFFF_Intrinsic<"fpnmsub">; 
     540  def int_ppc_fp2_fxmadd : PowerPC_FP2_FFFF_Intrinsic<"fxmadd">; 
     541  def int_ppc_fp2_fxnmadd : PowerPC_FP2_FFFF_Intrinsic<"fxnmadd">; 
     542  def int_ppc_fp2_fxmsub : PowerPC_FP2_FFFF_Intrinsic<"fxmsub">; 
     543  def int_ppc_fp2_fxnmsub : PowerPC_FP2_FFFF_Intrinsic<"fxnmsub">; 
     544  def int_ppc_fp2_fxcpmadd : PowerPC_FP2_FFFF_Intrinsic<"fxcpmadd">; 
     545  def int_ppc_fp2_fxcsmadd : PowerPC_FP2_FFFF_Intrinsic<"fxcsmadd">; 
     546  def int_ppc_fp2_fxcpnmadd : PowerPC_FP2_FFFF_Intrinsic<"fxcpnmadd">; 
     547  def int_ppc_fp2_fxcsnmadd : PowerPC_FP2_FFFF_Intrinsic<"fxcsnmadd">; 
     548  def int_ppc_fp2_fxcpmsub : PowerPC_FP2_FFFF_Intrinsic<"fxcpmsub">; 
     549  def int_ppc_fp2_fxcsmsub : PowerPC_FP2_FFFF_Intrinsic<"fxcsmsub">; 
     550  def int_ppc_fp2_fxcpnmsub : PowerPC_FP2_FFFF_Intrinsic<"fxcpnmsub">; 
     551  def int_ppc_fp2_fxcsnmsub : PowerPC_FP2_FFFF_Intrinsic<"fxcsnmsub">; 
     552   
     553  // Asymmetric multiply-add instructions 
     554  def int_ppc_fp2_fxcpnpma : PowerPC_FP2_FFFF_Intrinsic<"fxcpnpma">; 
     555  def int_ppc_fp2_fxcsnpma : PowerPC_FP2_FFFF_Intrinsic<"fxcsnpma">; 
     556  def int_ppc_fp2_fxcpnsma : PowerPC_FP2_FFFF_Intrinsic<"fxcpnsma">; 
     557  def int_ppc_fp2_fxcsnsma : PowerPC_FP2_FFFF_Intrinsic<"fxcsnsma">; 
     558   
     559  // Complex multiply-add instructions 
     560  def int_ppc_fp2_fxcxnpma : PowerPC_FP2_FFFF_Intrinsic<"fxcxnpma">; 
     561  def int_ppc_fp2_fxcxnsma : PowerPC_FP2_FFFF_Intrinsic<"fxcxnsma">; 
     562  def int_ppc_fp2_fxcxma : PowerPC_FP2_FFFF_Intrinsic<"fxcxma">; 
     563  def int_ppc_fp2_fxcxnms : PowerPC_FP2_FFFF_Intrinsic<"fxcxnms">; 
     564   
     565  // Select Instruction 
     566  def int_ppc_fp2_fpsel : PowerPC_FP2_FFFF_Intrinsic<"fpsel">; 
     567   
     568  // Convert and Round Instructions 
     569  def int_ppc_fp2_fpctiw : PowerPC_FP2_FF_Intrinsic<"fpctiw">; 
     570  def int_ppc_fp2_fpctiwz : PowerPC_FP2_FF_Intrinsic<"fpctiwz">; 
     571  def int_ppc_fp2_fprsp : PowerPC_FP2_FF_Intrinsic<"fprsp">; 
     572   
     573  // Move Instructions 
     574  def int_ppc_fp2_fpneg : PowerPC_FP2_FF_Intrinsic<"fpneg">; 
     575  def int_ppc_fp2_fpabs : PowerPC_FP2_FF_Intrinsic<"fpabs">; 
     576  def int_ppc_fp2_fpnabs : PowerPC_FP2_FF_Intrinsic<"fpnabs">; 
     577  def int_ppc_fp2_fxmr : PowerPC_FP2_FF_Intrinsic<"fxmr">; 
     578   
     579  // Load instructions 
     580  def int_ppc_fp2_lfpd : PowerPC_FP2_Load_Intrinsic<"lfpd">; 
     581  def int_ppc_fp2_lfps : PowerPC_FP2_Load_Intrinsic<"lfps">; 
     582  def int_ppc_fp2_lfxd : PowerPC_FP2_Load_Intrinsic<"lfxd">; 
     583  def int_ppc_fp2_lfxs : PowerPC_FP2_Load_Intrinsic<"lfxs">; 
     584 
     585  // Store instructions 
     586  def int_ppc_fp2_stfpd : PowerPC_FP2_Store_Intrinsic<"stfpd">; 
     587  def int_ppc_fp2_stfps : PowerPC_FP2_Store_Intrinsic<"stfps">; 
     588  def int_ppc_fp2_stfxd : PowerPC_FP2_Store_Intrinsic<"stfxd">; 
     589  def int_ppc_fp2_stfxs : PowerPC_FP2_Store_Intrinsic<"stfxs">; 
     590  def int_ppc_fp2_stfpiw : PowerPC_FP2_Store_Intrinsic<"stfpiw">; 
     591} 
     592 
     593//===----------------------------------------------------------------------===// 
     594// PowerPC QPX Intrinsics. 
     595// 
     596 
     597let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.". 
     598  /// PowerPC_QPX_Intrinsic - Base class for all QPX intrinsics. 
     599  class PowerPC_QPX_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types, 
     600                              list<LLVMType> param_types, 
     601                              list<IntrinsicProperty> properties> 
     602    : GCCBuiltin<!strconcat("__builtin_qpx_", GCCIntSuffix)>, 
     603      Intrinsic<ret_types, param_types, properties>; 
     604} 
     605 
     606//===----------------------------------------------------------------------===// 
     607// PowerPC QPX Intrinsic Class Definitions. 
     608// 
     609 
     610/// PowerPC_QPX_FF_Intrinsic - A PowerPC intrinsic that takes one v4f64 
     611/// vector and returns one.  These intrinsics have no side effects. 
     612class PowerPC_QPX_FF_Intrinsic<string GCCIntSuffix> 
     613  : PowerPC_QPX_Intrinsic<GCCIntSuffix, 
     614                          [llvm_v4f64_ty], [llvm_v4f64_ty], [IntrNoMem]>; 
     615 
     616/// PowerPC_QPX_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f64 
     617/// vectors and returns one.  These intrinsics have no side effects. 
     618class PowerPC_QPX_FFF_Intrinsic<string GCCIntSuffix> 
     619  : PowerPC_QPX_Intrinsic<GCCIntSuffix, 
     620                          [llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty], 
     621                          [IntrNoMem]>; 
     622 
     623/// PowerPC_QPX_FFFF_Intrinsic - A PowerPC intrinsic that takes three v4f64 
     624/// vectors and returns one.  These intrinsics have no side effects. 
     625class PowerPC_QPX_FFFF_Intrinsic<string GCCIntSuffix> 
     626  : PowerPC_QPX_Intrinsic<GCCIntSuffix, 
     627                          [llvm_v4f64_ty], 
     628                          [llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty], 
     629                          [IntrNoMem]>; 
     630 
     631/// PowerPC_QPX_Load_Intrinsic - A PowerPC intrinsic that takes a pointer 
     632/// and returns a v4f64. 
     633class PowerPC_QPX_Load_Intrinsic<string GCCIntSuffix> 
     634  : PowerPC_QPX_Intrinsic<GCCIntSuffix, 
     635                          [llvm_v4f64_ty], [llvm_ptr_ty], [IntrReadMem]>; 
     636 
     637/// PowerPC_QPX_Store_Intrinsic - A PowerPC intrinsic that takes a pointer 
     638/// and stores a v4f64. 
     639class PowerPC_QPX_Store_Intrinsic<string GCCIntSuffix> 
     640  : PowerPC_QPX_Intrinsic<GCCIntSuffix, 
     641                          [], [llvm_v4f64_ty, llvm_ptr_ty], []>; 
     642 
     643//===----------------------------------------------------------------------===// 
     644// PowerPC QPX Intrinsic Definitions. 
     645 
     646let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.". 
     647  // Add Instructions 
     648  def int_ppc_qpx_qvfadd : PowerPC_QPX_FFF_Intrinsic<"qvfadd">; 
     649  def int_ppc_qpx_qvfadds : PowerPC_QPX_FFF_Intrinsic<"qvfadds">; 
     650  def int_ppc_qpx_qvfsub : PowerPC_QPX_FFF_Intrinsic<"qvfsub">; 
     651  def int_ppc_qpx_qvfsubs : PowerPC_QPX_FFF_Intrinsic<"qvfsubs">; 
     652 
     653  // Estimate Instructions 
     654  def int_ppc_qpx_qvfre : PowerPC_QPX_FF_Intrinsic<"qvfre">; 
     655  def int_ppc_qpx_qvfres : PowerPC_QPX_FF_Intrinsic<"qvfres">; 
     656  def int_ppc_qpx_qvfrsqrte : PowerPC_QPX_FF_Intrinsic<"qvfrsqrte">; 
     657  def int_ppc_qpx_qvfrsqrtes : PowerPC_QPX_FF_Intrinsic<"qvfrsqrtes">; 
     658 
     659  // Multiply Instructions 
     660  def int_ppc_qpx_qvfmul : PowerPC_QPX_FFF_Intrinsic<"qvfmul">; 
     661  def int_ppc_qpx_qvfmuls : PowerPC_QPX_FFF_Intrinsic<"qvfmuls">; 
     662  def int_ppc_qpx_qvfxmul : PowerPC_QPX_FFF_Intrinsic<"qvfxmul">; 
     663  def int_ppc_qpx_qvfxmuls : PowerPC_QPX_FFF_Intrinsic<"qvfxmuls">; 
     664 
     665  // Multiply-add instructions 
     666  def int_ppc_qpx_qvfmadd : PowerPC_QPX_FFFF_Intrinsic<"qvfmadd">; 
     667  def int_ppc_qpx_qvfmadds : PowerPC_QPX_FFFF_Intrinsic<"qvfmadds">; 
     668  def int_ppc_qpx_qvfnmadd : PowerPC_QPX_FFFF_Intrinsic<"qvfnmadd">; 
     669  def int_ppc_qpx_qvfnmadds : PowerPC_QPX_FFFF_Intrinsic<"qvfnmadds">; 
     670  def int_ppc_qpx_qvfmsub : PowerPC_QPX_FFFF_Intrinsic<"qvfmsub">; 
     671  def int_ppc_qpx_qvfmsubs : PowerPC_QPX_FFFF_Intrinsic<"qvfmsubs">; 
     672  def int_ppc_qpx_qvfnmsub : PowerPC_QPX_FFFF_Intrinsic<"qvfnmsub">; 
     673  def int_ppc_qpx_qvfnmsubs : PowerPC_QPX_FFFF_Intrinsic<"qvfnmsubs">; 
     674  def int_ppc_qpx_qvfxmadd : PowerPC_QPX_FFFF_Intrinsic<"qvfxmadd">; 
     675  def int_ppc_qpx_qvfxmadds : PowerPC_QPX_FFFF_Intrinsic<"qvfxmadds">; 
     676  def int_ppc_qpx_qvfxxnpmadd : PowerPC_QPX_FFFF_Intrinsic<"qvfxxnpmadd">; 
     677  def int_ppc_qpx_qvfxxnpmadds : PowerPC_QPX_FFFF_Intrinsic<"qvfxxnpmadds">; 
     678  def int_ppc_qpx_qvfxxcpnmadd : PowerPC_QPX_FFFF_Intrinsic<"qvfxxcpnmadd">; 
     679  def int_ppc_qpx_qvfxxcpnmadds : PowerPC_QPX_FFFF_Intrinsic<"qvfxxcpnmadds">; 
     680  def int_ppc_qpx_qvfxxmadd : PowerPC_QPX_FFFF_Intrinsic<"qvfxxmadd">; 
     681  def int_ppc_qpx_qvfxxmadds : PowerPC_QPX_FFFF_Intrinsic<"qvfxxmadds">; 
     682 
     683  // Select Instruction 
     684  def int_ppc_qpx_qvfsel : PowerPC_QPX_FFFF_Intrinsic<"qvfsel">; 
     685 
     686  // Permute Instruction 
     687  def int_ppc_qpx_qvfperm : PowerPC_QPX_FFFF_Intrinsic<"qvfperm">; 
     688 
     689  // Convert and Round Instructions 
     690  def int_ppc_qpx_qvfctid : PowerPC_QPX_FF_Intrinsic<"qvfctid">; 
     691  def int_ppc_qpx_qvfctidu : PowerPC_QPX_FF_Intrinsic<"qvfctidu">; 
     692  def int_ppc_qpx_qvfctidz : PowerPC_QPX_FF_Intrinsic<"qvfctidz">; 
     693  def int_ppc_qpx_qvfctiduz : PowerPC_QPX_FF_Intrinsic<"qvfctiduz">; 
     694  def int_ppc_qpx_qvfctiw : PowerPC_QPX_FF_Intrinsic<"qvfctiw">; 
     695  def int_ppc_qpx_qvfctiwu : PowerPC_QPX_FF_Intrinsic<"qvfctiwu">; 
     696  def int_ppc_qpx_qvfctiwz : PowerPC_QPX_FF_Intrinsic<"qvfctiwz">; 
     697  def int_ppc_qpx_qvfctiwuz : PowerPC_QPX_FF_Intrinsic<"qvfctiwuz">; 
     698  def int_ppc_qpx_qvfcfid : PowerPC_QPX_FF_Intrinsic<"qvfcfid">; 
     699  def int_ppc_qpx_qvfcfidu : PowerPC_QPX_FF_Intrinsic<"qvfcfidu">; 
     700  def int_ppc_qpx_qvfcfids : PowerPC_QPX_FF_Intrinsic<"qvfcfids">; 
     701  def int_ppc_qpx_qvfcfidus : PowerPC_QPX_FF_Intrinsic<"qvfcfidus">; 
     702  def int_ppc_qpx_qvfrsp : PowerPC_QPX_FF_Intrinsic<"qvfrsp">; 
     703  def int_ppc_qpx_qvfriz : PowerPC_QPX_FF_Intrinsic<"qvfriz">; 
     704  def int_ppc_qpx_qvfrin : PowerPC_QPX_FF_Intrinsic<"qvfrin">; 
     705  def int_ppc_qpx_qvfrip : PowerPC_QPX_FF_Intrinsic<"qvfrip">; 
     706  def int_ppc_qpx_qvfrim : PowerPC_QPX_FF_Intrinsic<"qvfrim">; 
     707 
     708  // Move Instructions 
     709  def int_ppc_qpx_qvfneg : PowerPC_QPX_FF_Intrinsic<"qvfneg">; 
     710  def int_ppc_qpx_qvfabs : PowerPC_QPX_FF_Intrinsic<"qvfabs">; 
     711  def int_ppc_qpx_qvfnabs : PowerPC_QPX_FF_Intrinsic<"qvfnabs">; 
     712  def int_ppc_qpx_qvfcpsgn : PowerPC_QPX_FFF_Intrinsic<"qvfcpsgn">; 
     713 
     714  // Compare Instructions 
     715  def int_ppc_qpx_qvftstnan : PowerPC_QPX_FFF_Intrinsic<"qvftstnan">; 
     716  def int_ppc_qpx_qvfcmplt : PowerPC_QPX_FFF_Intrinsic<"qvfcmplt">; 
     717  def int_ppc_qpx_qvfcmpgt : PowerPC_QPX_FFF_Intrinsic<"qvfcmpgt">; 
     718  def int_ppc_qpx_qvfcmpeq : PowerPC_QPX_FFF_Intrinsic<"qvfcmpeq">; 
     719 
     720  // Load instructions 
     721  def int_ppc_qpx_qvlfd : PowerPC_QPX_Load_Intrinsic<"qvlfd">; 
     722  def int_ppc_qpx_qvlfda : PowerPC_QPX_Load_Intrinsic<"qvlfda">; 
     723  def int_ppc_qpx_qvlfs : PowerPC_QPX_Load_Intrinsic<"qvlfs">; 
     724  def int_ppc_qpx_qvlfsa : PowerPC_QPX_Load_Intrinsic<"qvlfsa">; 
     725 
     726  def int_ppc_qpx_qvlfcda : PowerPC_QPX_Load_Intrinsic<"qvlfcda">; 
     727  def int_ppc_qpx_qvlfcd : PowerPC_QPX_Load_Intrinsic<"qvlfcd">; 
     728  def int_ppc_qpx_qvlfcsa : PowerPC_QPX_Load_Intrinsic<"qvlfcsa">; 
     729  def int_ppc_qpx_qvlfcs : PowerPC_QPX_Load_Intrinsic<"qvlfcs">; 
     730  def int_ppc_qpx_qvlfiwaa : PowerPC_QPX_Load_Intrinsic<"qvlfiwaa">; 
     731  def int_ppc_qpx_qvlfiwa : PowerPC_QPX_Load_Intrinsic<"qvlfiwa">; 
     732  def int_ppc_qpx_qvlfiwza : PowerPC_QPX_Load_Intrinsic<"qvlfiwza">; 
     733  def int_ppc_qpx_qvlfiwz : PowerPC_QPX_Load_Intrinsic<"qvlfiwz">; 
     734 
     735  def int_ppc_qpx_qvlpcld : PowerPC_QPX_Load_Intrinsic<"qvlpcld">; 
     736  def int_ppc_qpx_qvlpcls : PowerPC_QPX_Load_Intrinsic<"qvlpcls">; 
     737  def int_ppc_qpx_qvlpcrd : PowerPC_QPX_Load_Intrinsic<"qvlpcrd">; 
     738  def int_ppc_qpx_qvlpcrs : PowerPC_QPX_Load_Intrinsic<"qvlpcrs">; 
     739 
     740  // Store instructions 
     741  def int_ppc_qpx_qvstfd : PowerPC_QPX_Store_Intrinsic<"qvstfd">; 
     742  def int_ppc_qpx_qvstfs : PowerPC_QPX_Store_Intrinsic<"qvstfs">; 
     743 
     744  def int_ppc_qpx_qvstfcda : PowerPC_QPX_Store_Intrinsic<"qvstfcda">; 
     745  def int_ppc_qpx_qvstfcd : PowerPC_QPX_Store_Intrinsic<"qvstfcd">; 
     746  def int_ppc_qpx_qvstfcsa : PowerPC_QPX_Store_Intrinsic<"qvstfcsa">; 
     747  def int_ppc_qpx_qvstfcs : PowerPC_QPX_Store_Intrinsic<"qvstfcs">; 
     748  def int_ppc_qpx_qvstfda : PowerPC_QPX_Store_Intrinsic<"qvstfda">; 
     749  def int_ppc_qpx_qvstfiwa : PowerPC_QPX_Store_Intrinsic<"qvstfiwa">; 
     750  def int_ppc_qpx_qvstfiw : PowerPC_QPX_Store_Intrinsic<"qvstfiw">; 
     751  def int_ppc_qpx_qvstfsa : PowerPC_QPX_Store_Intrinsic<"qvstfsa">; 
     752 
     753  // Misc. 
     754  def int_ppc_qpx_qvflogical : PowerPC_QPX_Intrinsic<"qvflogical", 
     755                          [llvm_v4f64_ty], 
     756                          [llvm_v4f64_ty, llvm_v4f64_ty, llvm_anyint_ty], 
     757                          [IntrNoMem]>; 
     758  def int_ppc_qpx_qvgpci : PowerPC_QPX_Intrinsic<"qvgpci", 
     759                          [llvm_v4f64_ty], [llvm_anyint_ty], [IntrNoMem]>; 
     760 
     761} 
     762 
  • lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

    diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    index e90373c..493cb14 100644
    a b  
    8989static cl::opt<bool> DisableSchedHeight( 
    9090  "disable-sched-height", cl::Hidden, cl::init(false), 
    9191  cl::desc("Disable scheduled-height priority in sched=list-ilp")); 
     92static cl::opt<float> SchedHeightCutoff( 
     93  "sched-height-cutoff", cl::Hidden, cl::init(0.5f), 
     94  cl::desc("Don't use scheduled-height priority in sched=list-ilp " 
     95           " when the fraction of computational units is below this")); 
    9296static cl::opt<bool> Disable2AddrHack( 
    9397  "disable-2addr-hack", cl::Hidden, cl::init(true), 
    9498  cl::desc("Disable scheduler's two-address hack")); 
     99static cl::opt<bool> DisableCallSpillCheck( 
     100  "disable-call-spill-check", cl::Hidden, cl::init(false), 
     101  cl::desc("Disable boosting call scheduling priority to prevent spilling")); 
    95102 
    96103static cl::opt<int> MaxReorderWindow( 
    97104  "max-sched-reorder", cl::Hidden, cl::init(6), 
     
    15891596  unsigned CurQueueId; 
    15901597  bool TracksRegPressure; 
    15911598  bool SrcOrder; 
     1599  float FracCompUnits; 
    15921600 
    15931601  // SUnits - The SUnits for the current graph. 
    15941602  std::vector<SUnit> *SUnits; 
     
    16191627                     const TargetRegisterInfo *tri, 
    16201628                     const TargetLowering *tli) 
    16211629    : SchedulingPriorityQueue(hasReadyFilter), 
    1622       CurQueueId(0), TracksRegPressure(tracksrp), SrcOrder(srcorder), 
     1630      CurQueueId(0), TracksRegPressure(tracksrp), 
     1631      SrcOrder(srcorder), FracCompUnits(0), 
    16231632      MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) { 
    16241633    if (TracksRegPressure) { 
    16251634      unsigned NumRC = TRI->getNumRegClasses(); 
     
    16821691 
    16831692  bool tracksRegPressure() const { return TracksRegPressure; } 
    16841693 
     1694  float fracCompUnits() const { return FracCompUnits; } 
     1695 
    16851696  void dumpRegPressure() const; 
    16861697 
     1698  bool CallMaySpill() const; 
     1699 
     1700  bool MayLoad(const SUnit *SU) const; 
     1701  bool MayStore(const SUnit *SU) const; 
     1702 
    16871703  bool HighRegPressure(const SUnit *SU) const; 
    16881704 
    16891705  bool MayReduceRegPressure(SUnit *SU) const; 
     
    17031719 
    17041720template<class SF> 
    17051721static SUnit *popFromQueueImpl(std::vector<SUnit*> &Q, SF &Picker) { 
    1706   std::vector<SUnit *>::iterator Best = Q.begin(); 
    1707   for (std::vector<SUnit *>::iterator I = llvm::next(Q.begin()), 
    1708          E = Q.end(); I != E; ++I) 
    1709     if (Picker(*Best, *I)) 
    1710       Best = I; 
     1722  std::vector<SUnit *>::iterator Best = std::max_element(Q.begin(), Q.end(), 
     1723                                                         Picker); 
    17111724  SUnit *V = *Best; 
    17121725  if (Best != prior(Q.end())) 
    17131726    std::swap(*Best, Q.back()); 
     
    19041917  } 
    19051918} 
    19061919 
     1920// If there are more registers allocated in a given class than there are 
     1921// callee-saved registers, then a call would have to spill those registers to 
     1922// the stack. 
     1923bool RegReductionPQBase::CallMaySpill() const { 
     1924  if (!RegPressure.size()) 
     1925    return false; 
     1926 
     1927  const uint16_t* CSR = TRI->getCalleeSavedRegs(&MF); 
     1928  for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), 
     1929         E = TRI->regclass_end(); I != E; ++I) { 
     1930    const TargetRegisterClass *RC = *I; 
     1931    unsigned Id = RC->getID(); 
     1932    unsigned RP = RegPressure[Id]; 
     1933 
     1934    unsigned Count = 0; 
     1935    for (const uint16_t *J = CSR; *J; ++J) { 
     1936      if (RC->contains(*J)) 
     1937        ++Count; 
     1938    } 
     1939 
     1940    if (Count > RP) 
     1941      return true; 
     1942  } 
     1943 
     1944  return false; 
     1945} 
     1946 
     1947bool RegReductionPQBase::MayLoad(const SUnit *SU) const { 
     1948  if (!SU->getNode()->isMachineOpcode())  
     1949    return false;  
     1950  
     1951  const MCInstrDesc &II = TII->get(SU->getNode()->getMachineOpcode());  
     1952  return II.mayLoad();  
     1953} 
     1954 
     1955bool RegReductionPQBase::MayStore(const SUnit *SU) const { 
     1956  if (!SU->getNode()->isMachineOpcode())  
     1957    return false;  
     1958  
     1959  const MCInstrDesc &II = TII->get(SU->getNode()->getMachineOpcode());  
     1960  return II.mayStore();  
     1961} 
     1962 
    19071963bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { 
    19081964  if (!TLI) 
    19091965    return false; 
     
    23552411} 
    23562412 
    23572413static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) { 
     2414  // FIXME: The scheduler currently does not adjust for the register 
     2415  // pressure from caller-saved registers across a call. Until it does, always 
     2416  // schedule a call over a non-load to prevent excess spilling. The cases for 
     2417  // loads is more complicated: a load which reduces register pressure should 
     2418  // be scheduled prior to the call, otherwise, it should come after the call. 
     2419  if (!DisableCallSpillCheck && SPQ->CallMaySpill()) { 
     2420    if (left->isCall && !right->isCall) { 
     2421      if (SPQ->MayLoad(right) && SPQ->MayReduceRegPressure(right)) 
     2422        return true; 
     2423      else 
     2424        return false; 
     2425    } else if (right->isCall && !left->isCall) { 
     2426      if (SPQ->MayLoad(left) && SPQ->MayReduceRegPressure(left)) 
     2427        return false; 
     2428      else 
     2429        return true; 
     2430    } 
     2431  } 
     2432 
    23582433  // Schedule physical register definitions close to their use. This is 
    23592434  // motivated by microarchitectures that can fuse cmp+jump macro-ops. But as 
    23602435  // long as shortening physreg live ranges is generally good, we can defer 
     
    26152690    } 
    26162691  } 
    26172692 
    2618   if (!DisableSchedHeight && left->getHeight() != right->getHeight()) { 
     2693  if (!DisableSchedHeight && SPQ->fracCompUnits() < SchedHeightCutoff && 
     2694      left->getHeight() != right->getHeight() && 
     2695      !((SPQ->MayLoad(left) || SPQ->MayStore(left)) && 
     2696       (SPQ->MayLoad(right) || SPQ->MayStore(right)))) { 
    26192697    int spread = (int)left->getHeight() - (int)right->getHeight(); 
    26202698    if (std::abs(spread) > MaxReorderWindow) 
    26212699      return left->getHeight() > right->getHeight(); 
     
    26412719      initVRegCycle(&sunits[i]); 
    26422720    } 
    26432721  } 
     2722 
     2723  unsigned NumCompUnits = 0; 
     2724  for (unsigned i = 0, e = sunits.size(); i != e; ++i) { 
     2725    if (sunits[i].isCall || MayLoad(&sunits[i]) || MayStore(&sunits[i])) 
     2726      ++NumCompUnits; 
     2727  } 
     2728 
     2729  FracCompUnits = (float) NumCompUnits / (float) sunits.size(); 
     2730 
     2731  DEBUG(dbgs() << "Block has " << NumCompUnits << " computational units" 
     2732                  " out of " << sunits.size() << " total units: " 
     2733               << 100.0f*FracCompUnits << "%\n"); 
    26442734} 
    26452735 
    26462736//===----------------------------------------------------------------------===// 
  • lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

    diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
    index 748668c..e99a317 100644
    a b  
    209209  unsigned NumOps = Node->getNumOperands(); 
    210210  if (Node->getOperand(NumOps-1).getValueType() == MVT::Other) 
    211211    Chain = Node->getOperand(NumOps-1).getNode(); 
     212  // FIXME: Check other children of the parent node. 
    212213  if (!Chain) 
    213214    return; 
    214215 
  • lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

    diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    index ab3ce48..14454c2 100644
    a b  
    1717#include "llvm/ADT/BitVector.h" 
    1818#include "llvm/ADT/PostOrderIterator.h" 
    1919#include "llvm/ADT/SmallSet.h" 
    20 #include "llvm/Analysis/AliasAnalysis.h" 
    2120#include "llvm/Analysis/ConstantFolding.h" 
    2221#include "llvm/Constants.h" 
    2322#include "llvm/CallingConv.h" 
     
    8483// %buffer = alloca [4096 x i8] 
    8584// %data = load [4096 x i8]* %argPtr 
    8685// store [4096 x i8] %data, [4096 x i8]* %buffer 
    87 static const unsigned MaxParallelChains = 64; 
     86static cl::opt<unsigned> 
     87MaxParallelChains("max-parallel-chains", cl::init(64), cl::Hidden, 
     88  cl::desc("The maximum number of parallel load/store chains generated from a" 
     89           " single sequence")); 
     90 
     91static cl::opt<unsigned> 
     92MaxLoadStoreReorder("max-load-store-reorder", cl::init(8), cl::Hidden, 
     93  cl::desc("The maximum number of parallel load/store chains to reorder" 
     94           " during selection-node generation")); 
     95 
     96static cl::opt<bool> 
     97NoReorderingPastStores("no-reordering-past-stores", cl::init(false), cl::Hidden, 
     98  cl::desc("Don't allow for reordering loads past stores or stores amongst" 
     99           " themselves during selection-node generation")); 
    88100 
    89101static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 
    90102                                      const SDValue *Parts, unsigned NumParts, 
     
    837849void SelectionDAGBuilder::clear() { 
    838850  NodeMap.clear(); 
    839851  UnusedArgNodeMap.clear(); 
    840   PendingLoads.clear(); 
     852  PendingMemOps.clear(); 
    841853  PendingExports.clear(); 
    842854  CurDebugLoc = DebugLoc(); 
    843855  HasTailCall = false; 
     
    858870/// a store or any other node that may need to be ordered after any 
    859871/// prior load instructions. 
    860872/// 
    861 SDValue SelectionDAGBuilder::getRoot() { 
    862   if (PendingLoads.empty()) 
     873SDValue SelectionDAGBuilder::getRoot(const Instruction *I, bool Final) { 
     874  // Not all PendingLoad items may need to be flushed. For example, 
     875  // if I, the instruction being visited, is a store, then we only 
     876  // need to flush loads that alias with it. 
     877  SmallVector<SDValue, 8> CritPendingMemOps; 
     878  if (I) { 
     879    for (SmallVector<SDValueWithLoc, 8>::iterator P = PendingMemOps.begin(); 
     880         P != PendingMemOps.end();) { 
     881      if (PendingMemOps.size() > MaxLoadStoreReorder || 
     882          ((P->IsWrite ? I->mayReadFromMemory() : I->mayWriteToMemory()) && 
     883          (!P->Loc.Ptr || (P->Loc.Ptr && 
     884            (AA->getModRefInfo(I, P->Loc) != AliasAnalysis::NoModRef))))) { 
     885        // Because of the way in which the scheduler interprets the DAG, 
     886        // placing stores at the end will cause them to tend to be scheduled in 
     887        // reverse order. That is probably not what we want. 
     888        CritPendingMemOps.insert(P->IsWrite ? CritPendingMemOps.begin() : 
     889                                 CritPendingMemOps.end(), P->Val); 
     890        P = PendingMemOps.erase(P); 
     891      } else 
     892        ++P; 
     893    } 
     894  } else { 
     895    for (SmallVector<SDValueWithLoc, 8>::iterator P = PendingMemOps.begin(); 
     896         P != PendingMemOps.end();) { 
     897      if (!Final || (Final && P->IsWrite)) { 
     898        CritPendingMemOps.insert(P->IsWrite ? CritPendingMemOps.begin() : 
     899                                 CritPendingMemOps.end(), P->Val); 
     900        P = PendingMemOps.erase(P); 
     901      } 
     902      else 
     903        ++P; 
     904    } 
     905  } 
     906 
     907  if (CritPendingMemOps.empty()) 
    863908    return DAG.getRoot(); 
    864909 
    865   if (PendingLoads.size() == 1) { 
    866     SDValue Root = PendingLoads[0]; 
    867     DAG.setRoot(Root); 
    868     PendingLoads.clear(); 
    869     return Root; 
    870   } 
     910  // Make sure that the current root is not lost (it could be a store or an 
     911  // intrinsic with other side effects). 
     912  CritPendingMemOps.append(1, DAG.getRoot()); 
    871913 
    872914  // Otherwise, we have to make a token factor node. 
    873915  SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 
    874                                &PendingLoads[0], PendingLoads.size()); 
    875   PendingLoads.clear(); 
     916                               &CritPendingMemOps[0], CritPendingMemOps.size()); 
     917  CritPendingMemOps.clear(); 
    876918  DAG.setRoot(Root); 
    877919  return Root; 
    878920} 
     
    882924/// to do this before emitting a terminator instruction. 
    883925/// 
    884926SDValue SelectionDAGBuilder::getControlRoot() { 
    885   SDValue Root = DAG.getRoot(); 
     927  SDValue Root = getRoot(0, true); 
    886928 
    887929  if (PendingExports.empty()) 
    888930    return Root; 
     
    32263268 
    32273269  SDValue Root; 
    32283270  bool ConstantMemory = false; 
    3229   if (I.isVolatile() || NumValues > MaxParallelChains) 
    3230     // Serialize volatile loads with other side effects. 
    3231     Root = getRoot(); 
    3232   else if (AA->pointsToConstantMemory( 
    3233              AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 
     3271  if (AA->pointsToConstantMemory( 
     3272         AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 
    32343273    // Do not serialize (non-volatile) loads of constant memory with anything. 
    32353274    Root = DAG.getEntryNode(); 
    32363275    ConstantMemory = true; 
    32373276  } else { 
    3238     // Do not serialize non-volatile loads against each other. 
    3239     Root = DAG.getRoot(); 
     3277    const Instruction *II = NumValues > MaxParallelChains ? 0 : &I; 
     3278    Root = getRoot(II); 
    32403279  } 
    32413280 
    32423281  SmallVector<SDValue, 4> Values(NumValues); 
     
    32523291    // avoid this case by converting large object/array copies to llvm.memcpy 
    32533292    // (MaxParallelChains should always remain as failsafe). 
    32543293    if (ChainI == MaxParallelChains) { 
    3255       assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 
    32563294      SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 
    32573295                                  MVT::Other, &Chains[0], ChainI); 
    32583296      Root = Chain; 
     
    32763314    if (isVolatile) 
    32773315      DAG.setRoot(Chain); 
    32783316    else 
    3279       PendingLoads.push_back(Chain); 
     3317      PendingMemOps.push_back(SDValueWithLoc(Chain, AA->getLocation(&I))); 
    32803318  } 
    32813319 
    32823320  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 
     
    33043342  SDValue Src = getValue(SrcV); 
    33053343  SDValue Ptr = getValue(PtrV); 
    33063344 
    3307   SDValue Root = getRoot(); 
     3345  SDValue Root = getRoot(NoReorderingPastStores ? 0 : &I); 
    33083346  SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 
    33093347                                          NumValues)); 
    33103348  EVT PtrVT = Ptr.getValueType(); 
     
    33353373                                  MVT::Other, &Chains[0], ChainI); 
    33363374  ++SDNodeOrder; 
    33373375  AssignOrderingToNode(StoreNode.getNode()); 
    3338   DAG.setRoot(StoreNode); 
     3376 
     3377  if (isVolatile) 
     3378    DAG.setRoot(StoreNode); 
     3379  else 
     3380    PendingMemOps.push_back(SDValueWithLoc(StoreNode, AA->getLocation(&I), 
     3381                                           true)); 
    33393382} 
    33403383 
    33413384static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 
     
    33673410  AtomicOrdering Order = I.getOrdering(); 
    33683411  SynchronizationScope Scope = I.getSynchScope(); 
    33693412 
    3370   SDValue InChain = getRoot(); 
     3413  SDValue InChain = getRoot(&I); 
    33713414 
    33723415  if (TLI.getInsertFencesForAtomic()) 
    33733416    InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 
     
    34143457  AtomicOrdering Order = I.getOrdering(); 
    34153458  SynchronizationScope Scope = I.getSynchScope(); 
    34163459 
    3417   SDValue InChain = getRoot(); 
     3460  SDValue InChain = getRoot(&I); 
    34183461 
    34193462  if (TLI.getInsertFencesForAtomic()) 
    34203463    InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 
     
    34543497  AtomicOrdering Order = I.getOrdering(); 
    34553498  SynchronizationScope Scope = I.getSynchScope(); 
    34563499 
    3457   SDValue InChain = getRoot(); 
     3500  SDValue InChain = getRoot(&I); 
    34583501 
    34593502  EVT VT = EVT::getEVT(I.getType()); 
    34603503 
     
    34843527  AtomicOrdering Order = I.getOrdering(); 
    34853528  SynchronizationScope Scope = I.getSynchScope(); 
    34863529 
    3487   SDValue InChain = getRoot(); 
     3530  SDValue InChain = getRoot(&I); 
    34883531 
    34893532  EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 
    34903533 
     
    35203563 
    35213564  // Build the operand list. 
    35223565  SmallVector<SDValue, 8> Ops; 
    3523   if (HasChain) {  // If this intrinsic has side-effects, chainify it. 
    3524     if (OnlyLoad) { 
    3525       // We don't need to serialize loads against other loads. 
    3526       Ops.push_back(DAG.getRoot()); 
    3527     } else { 
    3528       Ops.push_back(getRoot()); 
    3529     } 
    3530   } 
     3566  if (HasChain) // If this intrinsic has side-effects, chainify it. 
     3567    Ops.push_back(getRoot(&I)); 
    35313568 
    35323569  // Info is set by getTgtMemInstrinsic 
    35333570  TargetLowering::IntrinsicInfo Info; 
     
    35753612 
    35763613  if (HasChain) { 
    35773614    SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 
    3578     if (OnlyLoad) 
    3579       PendingLoads.push_back(Chain); 
    3580     else 
    3581       DAG.setRoot(Chain); 
     3615    PendingMemOps.push_back(SDValueWithLoc(Chain, !OnlyLoad)); 
    35823616  } 
    35833617 
    35843618  if (!I.getType()->isVoidTy()) { 
     
    45154549    SDValue Op3 = getValue(I.getArgOperand(2)); 
    45164550    unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 
    45174551    bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 
    4518     DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 
    4519                               MachinePointerInfo(I.getArgOperand(0)), 
     4552    DAG.setRoot(DAG.getMemcpy(getRoot(&I), dl, Op1, Op2, Op3, Align, isVol, 
     4553                              false, MachinePointerInfo(I.getArgOperand(0)), 
    45204554                              MachinePointerInfo(I.getArgOperand(1)))); 
    45214555    return 0; 
    45224556  } 
     
    45314565    SDValue Op3 = getValue(I.getArgOperand(2)); 
    45324566    unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 
    45334567    bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 
    4534     DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 
     4568    DAG.setRoot(DAG.getMemset(getRoot(&I), dl, Op1, Op2, Op3, Align, isVol, 
    45354569                              MachinePointerInfo(I.getArgOperand(0)))); 
     4570    // FIXME: When DAG.getMemset turns this into stores, they should really be 
     4571    // added to PendingMemOps. 
    45364572    return 0; 
    45374573  } 
    45384574  case Intrinsic::memmove: { 
     
    45484584    SDValue Op3 = getValue(I.getArgOperand(2)); 
    45494585    unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 
    45504586    bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 
    4551     DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 
     4587    DAG.setRoot(DAG.getMemmove(getRoot(&I), dl, Op1, Op2, Op3, Align, isVol, 
    45524588                               MachinePointerInfo(I.getArgOperand(0)), 
    45534589                               MachinePointerInfo(I.getArgOperand(1)))); 
    45544590    return 0; 
     
    51295165  case Intrinsic::prefetch: { 
    51305166    SDValue Ops[5]; 
    51315167    unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 
    5132     Ops[0] = getRoot(); 
     5168    Ops[0] = getRoot(&I); 
    51335169    Ops[1] = getValue(I.getArgOperand(0)); 
    51345170    Ops[2] = getValue(I.getArgOperand(1)); 
    51355171    Ops[3] = getValue(I.getArgOperand(2)); 
     
    52455281      MMI.setCurrentCallSite(0); 
    52465282    } 
    52475283 
    5248     // Both PendingLoads and PendingExports must be flushed here; 
     5284    // Both PendingMemOps and PendingExports must be flushed here; 
    52495285    // this call might not return. 
    52505286    (void)getRoot(); 
    52515287    DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 
     
    52635299    isTailCall = false; 
    52645300 
    52655301  TargetLowering:: 
    5266   CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 
     5302  CallLoweringInfo CLI(getRoot(dyn_cast<CallInst>(CS.getInstruction())), 
     5303                       RetTy, FTy, isTailCall, Callee, Args, DAG, 
    52675304                       getCurDebugLoc(), CS); 
    52685305  std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI); 
    52695306  assert((isTailCall || Result.second.getNode()) && 
     
    53045341 
    53055342    SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 
    53065343                                MVT::Other, &Chains[0], NumValues); 
    5307     PendingLoads.push_back(Chain); 
     5344    PendingMemOps.push_back(SDValueWithLoc(Chain)); 
    53085345 
    53095346    setValue(CS.getInstruction(), 
    53105347             DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 
     
    53925429                                        false /*isinvariant*/, 1 /* align=1 */); 
    53935430 
    53945431  if (!ConstantMemory) 
    5395     Builder.PendingLoads.push_back(LoadVal.getValue(1)); 
     5432    Builder.PendingMemOps.push_back(SelectionDAGBuilder::SDValueWithLoc( 
     5433                                     LoadVal.getValue(1), 
     5434                                     AliasAnalysis::Location(PtrVal))); 
    53965435  return LoadVal; 
    53975436} 
    53985437 
     
    54615500    } 
    54625501 
    54635502    if (ActuallyDoIt) { 
     5503      (void)getRoot(&I); // flush any conflicting stores 
    54645504      SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 
    54655505      SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 
    54665506 
     
    63276367 
    63286368void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 
    63296369  DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 
    6330                           MVT::Other, getRoot(), 
     6370                          MVT::Other, getRoot(&I), 
    63316371                          getValue(I.getArgOperand(0)), 
    63326372                          DAG.getSrcValue(I.getArgOperand(0)))); 
    63336373} 
     
    63356375void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 
    63366376  const TargetData &TD = *TLI.getTargetData(); 
    63376377  SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 
    6338                            getRoot(), getValue(I.getOperand(0)), 
     6378                           getRoot(&I), getValue(I.getOperand(0)), 
    63396379                           DAG.getSrcValue(I.getOperand(0)), 
    63406380                           TD.getABITypeAlignment(I.getType())); 
    63416381  setValue(&I, V); 
     
    63446384 
    63456385void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 
    63466386  DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 
    6347                           MVT::Other, getRoot(), 
     6387                          MVT::Other, getRoot(&I), 
    63486388                          getValue(I.getArgOperand(0)), 
    63496389                          DAG.getSrcValue(I.getArgOperand(0)))); 
    63506390} 
    63516391 
    63526392void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 
    63536393  DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 
    6354                           MVT::Other, getRoot(), 
     6394                          MVT::Other, getRoot(&I), 
    63556395                          getValue(I.getArgOperand(0)), 
    63566396                          getValue(I.getArgOperand(1)), 
    63576397                          DAG.getSrcValue(I.getArgOperand(0)), 
     
    66476687 
    66486688  // Call the target to set up the argument values. 
    66496689  SmallVector<SDValue, 8> InVals; 
    6650   SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 
     6690  SDValue NewRoot = TLI.LowerFormalArguments(SDB->getRoot(0, true), F.getCallingConv(), 
    66516691                                             F.isVarArg(), Ins, 
    66526692                                             dl, DAG, InVals); 
    66536693 
  • lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

    diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
    index d0fde6f..872a033 100644
    a b  
    1616 
    1717#include "llvm/Constants.h" 
    1818#include "llvm/CodeGen/SelectionDAG.h" 
     19#include "llvm/Analysis/AliasAnalysis.h" 
    1920#include "llvm/ADT/APInt.h" 
    2021#include "llvm/ADT/DenseMap.h" 
    2122#include "llvm/CodeGen/SelectionDAGNodes.h" 
     
    2627 
    2728namespace llvm { 
    2829 
    29 class AliasAnalysis; 
    3030class AllocaInst; 
    3131class BasicBlock; 
    3232class BitCastInst; 
     
    108108  DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap; 
    109109 
    110110public: 
    111   /// PendingLoads - Loads are not emitted to the program immediately.  We bunch 
    112   /// them up and then emit token factor nodes when possible.  This allows us to 
    113   /// get simple disambiguation between loads without worrying about alias 
    114   /// analysis. 
    115   SmallVector<SDValue, 8> PendingLoads; 
     111  /// PendingMemOps - Loads and stores are not emitted to the program 
     112  /// immediately.  We bunch them up and then emit token factor nodes when 
     113  /// possible. 
     114  struct SDValueWithLoc { 
     115    SDValue Val; 
     116    AliasAnalysis::Location Loc; 
     117    bool IsWrite; 
     118 
     119    SDValueWithLoc(SDValue v, bool w = false) : Val(v), IsWrite(w) {} 
     120    SDValueWithLoc(SDValue v, AliasAnalysis::Location l, bool w = false) 
     121      : Val(v), Loc(l), IsWrite(w) {} 
     122  }; 
     123 
     124  SmallVector<SDValueWithLoc, 8> PendingMemOps; 
    116125private: 
    117126 
    118127  /// PendingExports - CopyToReg nodes that copy values to virtual registers 
     
    348357  void clearDanglingDebugInfo(); 
    349358 
    350359  /// getRoot - Return the current virtual root of the Selection DAG, 
    351   /// flushing any PendingLoad items. This must be done before emitting 
     360  /// flushing any PendingMemOps items. This must be done before emitting 
    352361  /// a store or any other node that may need to be ordered after any 
    353362  /// prior load instructions. 
    354363  /// 
    355   SDValue getRoot(); 
     364  SDValue getRoot(const Instruction *I = 0, bool Final = false); 
    356365 
    357366  /// getControlRoot - Similar to getRoot, but instead of flushing all the 
    358   /// PendingLoad items, flush all the PendingExports items. It is necessary 
     367  /// PendingMemOps items, flush all the PendingExports items. It is necessary 
    359368  /// to do this before emitting a terminator instruction. 
    360369  /// 
    361370  SDValue getControlRoot(); 
  • lib/Support/APFloat.cpp

    diff --git a/lib/Support/APFloat.cpp b/lib/Support/APFloat.cpp
    index 409d4fb..5141125 100644
    a b  
    6161  // The PowerPC format consists of two doubles.  It does not map cleanly 
    6262  // onto the usual format above.  For now only storage of constants of 
    6363  // this type is supported, no arithmetic. 
    64   const fltSemantics APFloat::PPCDoubleDouble = { 1023, -1022, 106, false }; 
     64  // FIXME: arithmeticOK should really be false here... 
     65  const fltSemantics APFloat::PPCDoubleDouble = { 1023, -1022, 106, true }; 
    6566 
    6667  /* A tight upper bound on number of parts required to hold the value 
    6768     pow(5, power) is 
  • lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp

    diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
    index 61d23ce..df7b9d5 100644
    a b  
    109109  printOperand(MI, OpNo+1, O); 
    110110} 
    111111 
     112void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo, 
     113                                       raw_ostream &O) { 
     114  unsigned char Value = MI->getOperand(OpNo).getImm(); 
     115  assert(Value <= 3 && "Invalid u2imm argument!"); 
     116  O << (unsigned int)Value; 
     117} 
     118 
    112119void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo, 
    113120                                       raw_ostream &O) { 
    114121  char Value = MI->getOperand(OpNo).getImm(); 
     
    130137  O << (unsigned int)Value; 
    131138} 
    132139 
     140void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo, 
     141                                        raw_ostream &O) { 
     142  unsigned short Value = MI->getOperand(OpNo).getImm(); 
     143  assert(Value <= 4095 && "Invalid u12imm argument!"); 
     144  O << (unsigned short)Value; 
     145} 
     146 
    133147void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo, 
    134148                                        raw_ostream &O) { 
    135149  O << (short)MI->getOperand(OpNo).getImm(); 
     
    233247  case 'f': 
    234248  case 'v': return RegName + 1; 
    235249  case 'c': if (RegName[1] == 'r') return RegName + 2; 
     250  case 'd': if (RegName[1] == 'f') return RegName + 2; // for FP2 
     251  case 'q': if (RegName[1] == 'f') return RegName + 2; // for QPX  
    236252  } 
    237253   
    238254  return RegName; 
  • lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h

    diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
    index 73fd534..daf3d92 100644
    a b  
    4444  void printPredicateOperand(const MCInst *MI, unsigned OpNo, 
    4545                             raw_ostream &O, const char *Modifier); 
    4646 
    47  
     47  void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 
    4848  void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 
    4949  void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 
    5050  void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 
     51  void printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 
    5152  void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 
    5253  void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 
    5354  void printS16X4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 
  • lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h

    diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h b/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h
    index 9c975c0..ae2483a 100644
    a b  
    6060  case R29:  case X29:  case F29:  case V29: case CR7GT: return 29; 
    6161  case R30:  case X30:  case F30:  case V30: case CR7EQ: return 30; 
    6262  case R31:  case X31:  case F31:  case V31: case CR7UN: return 31; 
     63  case DF0 :  case QF0 : return  0; 
     64  case DF1 :  case QF1 : return  1; 
     65  case DF2 :  case QF2 : return  2; 
     66  case DF3 :  case QF3 : return  3; 
     67  case DF4 :  case QF4 : return  4; 
     68  case DF5 :  case QF5 : return  5; 
     69  case DF6 :  case QF6 : return  6; 
     70  case DF7 :  case QF7 : return  7; 
     71  case DF8 :  case QF8 : return  8; 
     72  case DF9 :  case QF9 : return  9; 
     73  case DF10:  case QF10: return 10; 
     74  case DF11:  case QF11: return 11; 
     75  case DF12:  case QF12: return 12; 
     76  case DF13:  case QF13: return 13; 
     77  case DF14:  case QF14: return 14; 
     78  case DF15:  case QF15: return 15; 
     79  case DF16:  case QF16: return 16; 
     80  case DF17:  case QF17: return 17; 
     81  case DF18:  case QF18: return 18; 
     82  case DF19:  case QF19: return 19; 
     83  case DF20:  case QF20: return 20; 
     84  case DF21:  case QF21: return 21; 
     85  case DF22:  case QF22: return 22; 
     86  case DF23:  case QF23: return 23; 
     87  case DF24:  case QF24: return 24; 
     88  case DF25:  case QF25: return 25; 
     89  case DF26:  case QF26: return 26; 
     90  case DF27:  case QF27: return 27; 
     91  case DF28:  case QF28: return 28; 
     92  case DF29:  case QF29: return 29; 
     93  case DF30:  case QF30: return 30; 
     94  case DF31:  case QF31: return 31; 
    6395  default: 
    6496    llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!"); 
    6597  } 
  • lib/Target/PowerPC/PPC.td

    diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
    index c554d39..7327d28 100644
    a b  
    4242                              "Enable 64-bit registers usage for ppc32 [beta]">; 
    4343def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true", 
    4444                                        "Enable Altivec instructions">; 
     45def FeatureFP2       : SubtargetFeature<"fp2","HasFP2", "true", 
     46                              "Enable FP2 (Double Hummer) instructions [beta]">; 
    4547def FeatureGPUL      : SubtargetFeature<"gpul","IsGigaProcessor", "true", 
    4648                                        "Enable GPUL instructions">; 
    4749def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true", 
     
    5052                                        "Enable the stfiwx instruction">; 
    5153def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true", 
    5254                                        "Enable Book E instructions">; 
     55def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true", 
     56                                        "Enable QPX instructions [beta]">; 
    5357 
    5458//===----------------------------------------------------------------------===// 
    5559// Register File Description 
     
    6569 
    6670def : Processor<"generic", G3Itineraries, [Directive32]>; 
    6771def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>; 
     72def : Processor<"440fp2", PPC440Itineraries, // BG/L 
     73                          [Directive440, FeatureFSqrt, FeatureSTFIWX, 
     74                           FeatureFP2]>; 
     75def : Processor<"440d", PPC440Itineraries,   // BG/L 
     76                          [Directive440, FeatureFSqrt, FeatureSTFIWX, 
     77                           FeatureFP2]>; 
    6878def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>; 
     79def : Processor<"450fp2", PPC440Itineraries, // BG/P 
     80                          [Directive440, FeatureFSqrt, FeatureSTFIWX, 
     81                           FeatureFP2]>; 
     82def : Processor<"450d", PPC440Itineraries,   // BG/P 
     83                          [Directive440, FeatureFSqrt, FeatureSTFIWX, 
     84                           FeatureFP2]>; 
    6985def : Processor<"601", G3Itineraries, [Directive601]>; 
    7086def : Processor<"602", G3Itineraries, [Directive602]>; 
    7187def : Processor<"603", G3Itineraries, [Directive603]>; 
     
    92108                                          FeatureFSqrt, FeatureSTFIWX, 
    93109                                          Feature64Bit 
    94110                                      /*, Feature64BitRegs */]>; 
     111def : Processor<"a2q", PPCA2Itineraries, // BG/Q 
     112                          [DirectiveA2, FeatureBookE, FeatureFSqrt, 
     113                           FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */, 
     114                           FeatureQPX]>; 
    95115def : Processor<"ppc", G3Itineraries, [Directive32]>; 
    96116def : Processor<"ppc64", G5Itineraries, 
    97117                  [Directive64, FeatureAltivec, 
  • lib/Target/PowerPC/PPCAsmPrinter.cpp

    diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
    index fb7aa71..4059f3d 100644
    a b  
    137137    case 'f': 
    138138    case 'v': return RegName + 1; 
    139139    case 'c': if (RegName[1] == 'r') return RegName + 2; 
     140    case 'd': if (RegName[1] == 'f') return RegName + 2; // for FP2 
     141    case 'q': if (RegName[1] == 'f') return RegName + 2; // for QPX 
    140142  } 
    141143   
    142144  return RegName; 
  • lib/Target/PowerPC/PPCCallingConv.td

    diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td
    index b2b5364..c68312e 100644
    a b  
    2323   
    2424  CCIfType<[f32], CCAssignToReg<[F1]>>, 
    2525  CCIfType<[f64], CCAssignToReg<[F1, F2]>>, 
     26  CCIfType<[v2f64], CCAssignToReg<[DF1, DF2]>>, 
     27  CCIfType<[v4f64], CCAssignToReg<[QF1, QF2]>>, 
    2628   
    2729  // Vector types are always returned in V2. 
    2830  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> 
     
    4143  // Common sub-targets passes FP values in F1 - F13 
    4244  CCIfType<[f32, f64],  
    4345           CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>, 
    44             
     46  CCIfType<[v2f64],  
     47           CCAssignToReg<[DF1,DF2,DF3,DF4,DF5,DF6,DF7, 
     48                          DF8,DF9,DF10,DF11,DF12,DF13]>>, 
     49  CCIfType<[v4f64],  
     50           CCAssignToReg<[QF1,QF2,QF3,QF4,QF5,QF6,QF7, 
     51                          QF8,QF9,QF10,QF11,QF12,QF13]>>, 
     52  
    4553  // The first 12 Vector arguments are passed in altivec registers. 
    4654  CCIfType<[v16i8, v8i16, v4i32, v4f32], 
    4755              CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>> 
     
    7684   
    7785  // FP values are passed in F1 - F8. 
    7886  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>, 
     87  CCIfType<[v2f64], CCAssignToReg<[DF1, DF2, DF3, DF4, DF5, DF6, DF7, DF8]>>, 
     88  CCIfType<[v4f64], CCAssignToReg<[QF1, QF2, QF3, QF4, QF5, QF6, QF7, QF8]>>, 
    7989 
    8090  // Split arguments have an alignment of 8 bytes on the stack. 
    8191  CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>, 
     
    8595  // Floats are stored in double precision format, thus they have the same 
    8696  // alignment and size as doubles. 
    8797  CCIfType<[f32,f64], CCAssignToStack<8, 8>>,   
     98  CCIfType<[v2f64], CCAssignToStack<16, 16>>, 
     99  CCIfType<[v4f64], CCAssignToStack<32, 32>>, 
    88100 
    89101  // Vectors get 16-byte stack slots that are 16-byte aligned. 
    90102  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>> 
  • lib/Target/PowerPC/PPCFrameLowering.cpp

    diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp
    index be172c2..1d3bfc8 100644
    a b  
    714714  } 
    715715} 
    716716 
    717 static bool spillsCR(const MachineFunction &MF) { 
    718   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 
    719   return FuncInfo->isCRSpilled(); 
    720 } 
     717// FIXME: (commented out to prevent unused function warnings), 
     718// see comment at the end of processFunctionBeforeCalleeSavedScan 
     719//static bool spillsCR(const MachineFunction &MF) { 
     720//  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 
     721//  return FuncInfo->isCRSpilled(); 
     722//} 
    721723 
    722724/// MustSaveLR - Return true if this function requires that we save the LR 
    723725/// register onto the stack in the prolog and restore it in the epilog of the 
     
    774776  // FIXME: doesn't detect whether or not we need to spill vXX, which requires 
    775777  //        r0 for now. 
    776778 
    777   if (RegInfo->requiresRegisterScavenging(MF)) 
    778     if (needsFP(MF) || spillsCR(MF)) { 
     779  if (RegInfo->requiresRegisterScavenging(MF)) { 
     780    // FIXME: this check does not capture all necessary cases, 
     781    // it needs to be improved! Specifically, there is a problem when a 
     782    // scavenged register is needed for a large-offset indexed load/store. 
     783    // For now, always allocate the slot. 
     784    // if (needsFP(MF) || spillsCR(MF)) { 
    779785      const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 
    780786      const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 
    781787      const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 
    782788      RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 
    783789                                                         RC->getAlignment(), 
    784790                                                         false)); 
     791    // FIXME: see comment above 
     792    // } 
    785793    } 
    786794} 
    787795 
  • lib/Target/PowerPC/PPCFrameLowering.h

    diff --git a/lib/Target/PowerPC/PPCFrameLowering.h b/lib/Target/PowerPC/PPCFrameLowering.h
    index d708541..e865111 100644
    a b  
    2727 
    2828public: 
    2929  PPCFrameLowering(const PPCSubtarget &sti) 
    30     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0), 
     30    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 
     31        sti.hasQPX() ? 32 : 16, 0), 
    3132      Subtarget(sti) { 
    3233  } 
    3334 
  • lib/Target/PowerPC/PPCISelLowering.cpp

    diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
    index 46d656c..655f4ed 100644
    a b  
    388388    setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 
    389389  } 
    390390 
     391  if (TM.getSubtarget<PPCSubtarget>().hasFP2()) { 
     392    setOperationAction(ISD::FADD, MVT::v2f64, Legal); 
     393    setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 
     394    setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 
     395    setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 
     396    setOperationAction(ISD::FREM, MVT::v2f64, Expand); 
     397 
     398    setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 
     399    setOperationAction(ISD::FGETSIGN, MVT::v2f64, Expand); 
     400 
     401    setOperationAction(ISD::LOAD  , MVT::v2f64, Legal); 
     402    setOperationAction(ISD::STORE , MVT::v2f64, Legal); 
     403    setOperationAction(ISD::STORE , MVT::v2i32, Legal); 
     404 
     405    setOperationAction(ISD::SELECT, MVT::v2f64, Expand); 
     406    setOperationAction(ISD::VSELECT, MVT::v2f64, Expand); 
     407 
     408    setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v2f64, Legal); 
     409    setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v2f64, Expand); 
     410    setOperationAction(ISD::CONCAT_VECTORS , MVT::v2f64, Expand); 
     411    setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v2f64, Expand); 
     412    setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v2f64, Legal); 
     413    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); 
     414    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 
     415 
     416    setOperationAction(ISD::FP_TO_SINT , MVT::v2f64, Legal); 
     417    setOperationAction(ISD::FP_TO_UINT , MVT::v2f64, Expand); 
     418 
     419    setOperationAction(ISD::FP_ROUND , MVT::v2f64, Expand); 
     420    setOperationAction(ISD::FP_ROUND_INREG , MVT::v2f64, Expand); 
     421    setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); 
     422 
     423    setOperationAction(ISD::FNEG , MVT::v2f64, Legal); 
     424    setOperationAction(ISD::FABS , MVT::v2f64, Legal); 
     425    setOperationAction(ISD::FSQRT , MVT::v2f64, Expand); 
     426    setOperationAction(ISD::FSIN , MVT::v2f64, Expand); 
     427    setOperationAction(ISD::FCOS , MVT::v2f64, Expand); 
     428    setOperationAction(ISD::FPOWI , MVT::v2f64, Expand); 
     429    setOperationAction(ISD::FPOW , MVT::v2f64, Expand); 
     430    setOperationAction(ISD::FLOG , MVT::v2f64, Expand); 
     431    setOperationAction(ISD::FLOG2 , MVT::v2f64, Expand); 
     432    setOperationAction(ISD::FLOG10 , MVT::v2f64, Expand); 
     433    setOperationAction(ISD::FEXP , MVT::v2f64, Expand); 
     434    setOperationAction(ISD::FEXP2 , MVT::v2f64, Expand); 
     435    setOperationAction(ISD::FCEIL , MVT::v2f64, Expand); 
     436    setOperationAction(ISD::FTRUNC , MVT::v2f64, Expand); 
     437    setOperationAction(ISD::FRINT , MVT::v2f64, Expand); 
     438    setOperationAction(ISD::FNEARBYINT , MVT::v2f64, Expand); 
     439    setOperationAction(ISD::FFLOOR , MVT::v2f64, Expand); 
     440 
     441    addRegisterClass(MVT::v2f64, &PPC::DFRCRegClass); 
     442  } else if (TM.getSubtarget<PPCSubtarget>().hasQPX()) { 
     443    setOperationAction(ISD::FADD, MVT::v4f64, Legal); 
     444    setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 
     445    setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 
     446    setOperationAction(ISD::FDIV, MVT::v4f64, Expand); 
     447    setOperationAction(ISD::FREM, MVT::v4f64, Expand); 
     448 
     449    setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Expand); 
     450    setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); 
     451 
     452    setOperationAction(ISD::LOAD  , MVT::v4f64, Legal); 
     453    setOperationAction(ISD::STORE , MVT::v4f64, Legal); 
     454 
     455    setOperationAction(ISD::SELECT, MVT::v4f64, Expand); 
     456    setOperationAction(ISD::VSELECT, MVT::v4f64, Expand); 
     457 
     458    setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal); 
     459    setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand); 
     460    setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); 
     461    setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand); 
     462    setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom); 
     463    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal); 
     464    setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); 
     465 
     466    setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal); 
     467    setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand); 
     468 
     469    setOperationAction(ISD::FP_ROUND , MVT::v4f64, Expand); 
     470    setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f64, Expand); 
     471    setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Expand); 
     472 
     473    setOperationAction(ISD::FNEG , MVT::v4f64, Legal); 
     474    setOperationAction(ISD::FABS , MVT::v4f64, Legal); 
     475    setOperationAction(ISD::FSQRT , MVT::v4f64, Expand); 
     476    setOperationAction(ISD::FSIN , MVT::v4f64, Expand); 
     477    setOperationAction(ISD::FCOS , MVT::v4f64, Expand); 
     478    setOperationAction(ISD::FPOWI , MVT::v4f64, Expand); 
     479    setOperationAction(ISD::FPOW , MVT::v4f64, Expand); 
     480    setOperationAction(ISD::FLOG , MVT::v4f64, Expand); 
     481    setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand); 
     482    setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand); 
     483    setOperationAction(ISD::FEXP , MVT::v4f64, Expand); 
     484    setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand); 
     485    setOperationAction(ISD::FCEIL , MVT::v4f64, Expand); 
     486    setOperationAction(ISD::FTRUNC , MVT::v4f64, Expand); 
     487    setOperationAction(ISD::FRINT , MVT::v4f64, Expand); 
     488    setOperationAction(ISD::FNEARBYINT , MVT::v4f64, Expand); 
     489    setOperationAction(ISD::FFLOOR , MVT::v4f64, Expand); 
     490 
     491    addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass); 
     492  } 
     493 
    391494  if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) 
    392495    setOperationAction(ISD::PREFETCH, MVT::Other, Legal); 
    393496 
     
    504607  case PPCISD::FADDRTZ:         return "PPCISD::FADDRTZ"; 
    505608  case PPCISD::MTFSF:           return "PPCISD::MTFSF"; 
    506609  case PPCISD::TC_RETURN:       return "PPCISD::TC_RETURN"; 
     610  case PPCISD::QVFPERM:         return "PPCISD::QVFPERM"; 
     611  case PPCISD::QVGPCI:          return "PPCISD::QVGPCI"; 
     612  case PPCISD::QVALIGNI:        return "PPCISD::QVALIGNI"; 
     613  case PPCISD::QVESPLATI:       return "PPCISD::QVESPLATI"; 
    507614  } 
    508615} 
    509616 
     
    534641  return Op < 0 || Op == Val; 
    535642} 
    536643 
     644static bool isAltivecRegisterType(EVT e) { 
     645  return e == MVT::v16i8 || e == MVT::v8i16 
     646         || e == MVT::v4i32 || e == MVT::v4f32; 
     647} 
     648 
    537649/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 
    538650/// VPKUHUM instruction. 
    539651bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 
     652  if (!isAltivecRegisterType(N->getValueType(0))) 
     653    return false; 
     654 
    540655  if (!isUnary) { 
    541656    for (unsigned i = 0; i != 16; ++i) 
    542657      if (!isConstantOrUndef(N->getMaskElt(i),  i*2+1)) 
     
    553668/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 
    554669/// VPKUWUM instruction. 
    555670bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 
     671  if (!isAltivecRegisterType(N->getValueType(0))) 
     672    return false; 
     673 
    556674  if (!isUnary) { 
    557675    for (unsigned i = 0; i != 16; i += 2) 
    558676      if (!isConstantOrUndef(N->getMaskElt(i  ),  i*2+2) || 
     
    593711/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 
    594712bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 
    595713                             bool isUnary) { 
     714  if (!isAltivecRegisterType(N->getValueType(0))) 
     715    return false; 
     716 
    596717  if (!isUnary) 
    597718    return isVMerge(N, UnitSize, 8, 24); 
    598719  return isVMerge(N, UnitSize, 8, 8); 
     
    602723/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 
    603724bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 
    604725                             bool isUnary) { 
     726  if (!isAltivecRegisterType(N->getValueType(0))) 
     727    return false; 
     728 
    605729  if (!isUnary) 
    606730    return isVMerge(N, UnitSize, 0, 16); 
    607731  return isVMerge(N, UnitSize, 0, 0); 
     
    611735/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 
    612736/// amount, otherwise return -1. 
    613737int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 
     738  if (!isAltivecRegisterType(N->getValueType(0))) 
     739    return -1; 
     740 
    614741  assert(N->getValueType(0) == MVT::v16i8 && 
    615742         "PPC only supports shuffles by bytes!"); 
    616743 
     
    647774/// specifies a splat of a single element that is suitable for input to 
    648775/// VSPLTB/VSPLTH/VSPLTW. 
    649776bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 
     777  if (!isAltivecRegisterType(N->getValueType(0))) 
     778    return false; 
     779 
    650780  assert(N->getValueType(0) == MVT::v16i8 && 
    651781         (EltSize == 1 || EltSize == 2 || EltSize == 4)); 
    652782 
     
    810940  return SDValue(); 
    811941} 
    812942 
     943/// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift 
     944/// amount, otherwise return -1. 
     945int PPC::isQVALIGNIShuffleMask(SDNode *N) { 
     946  if (N->getValueType(0) != MVT::v4f64) 
     947    return -1; 
     948 
     949  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 
     950 
     951  // Find the first non-undef value in the shuffle mask. 
     952  unsigned i; 
     953  for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i) 
     954    /*search*/; 
     955 
     956  if (i == 4) return -1;  // all undef. 
     957 
     958  // Otherwise, check to see if the rest of the elements are consecutively 
     959  // numbered from this value. 
     960  unsigned ShiftAmt = SVOp->getMaskElt(i); 
     961  if (ShiftAmt < i) return -1; 
     962  ShiftAmt -= i; 
     963 
     964  // Check the rest of the elements to see if they are consecutive. 
     965  for (++i; i != 4; ++i) 
     966    if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 
     967      return -1; 
     968 
     969  return ShiftAmt; 
     970} 
     971 
    813972//===----------------------------------------------------------------------===// 
    814973//  Addressing Mode Selection 
    815974//===----------------------------------------------------------------------===// 
     
    17361895        case MVT::v4f32: 
    17371896          RC = &PPC::VRRCRegClass; 
    17381897          break; 
     1898        case MVT::v2f64: 
     1899          RC = &PPC::DFRCRegClass; 
     1900          break; 
     1901        case MVT::v4f64: 
     1902          RC = &PPC::QFRCRegClass; 
     1903          break; 
    17391904      } 
    17401905 
    17411906      // Transform the arguments stored in physical registers into virtual ones. 
     
    40114176  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 
    40124177  assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 
    40134178 
     4179  const TargetMachine &TM = getTargetMachine(); 
     4180  if (TM.getSubtarget<PPCSubtarget>().hasFP2() || 
     4181      TM.getSubtarget<PPCSubtarget>().hasQPX()) { 
     4182    return SDValue(); 
     4183  } 
     4184 
    40144185  // Check if this is a splat of a constant value. 
    40154186  APInt APSplatBits, APSplatUndef; 
    40164187  unsigned SplatBitSize; 
     
    42554426  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 
    42564427  EVT VT = Op.getValueType(); 
    42574428 
     4429  const TargetMachine &TM = getTargetMachine(); 
     4430  if (TM.getSubtarget<PPCSubtarget>().hasFP2()) { 
     4431    return SDValue(); 
     4432  } else if (TM.getSubtarget<PPCSubtarget>().hasQPX()) { 
     4433    if (VT.getVectorNumElements() != 4) 
     4434      return SDValue(); 
     4435 
     4436    if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 
     4437 
     4438    int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp); 
     4439    if (AlignIdx != -1) { 
     4440      return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2, 
     4441                         DAG.getConstant(AlignIdx, MVT::i32)); 
     4442    } else if (SVOp->isSplat()) { 
     4443      int SplatIdx = SVOp->getSplatIndex(); 
     4444      if (SplatIdx >= 4) { 
     4445        std::swap(V1, V2); 
     4446        SplatIdx -= 4; 
     4447      } 
     4448 
     4449      // FIXME: If SplatIdx == 0 and the input came from a load, then there is 
     4450      // nothing to do. 
     4451 
     4452      return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1, 
     4453                         DAG.getConstant(SplatIdx, MVT::i32)); 
     4454    } 
     4455 
     4456    // Lower this into a qvgpci/qvfperm pair. 
     4457 
     4458    // Compute the qvgpci literal 
     4459    unsigned idx = 0; 
     4460    for (unsigned i = 0; i < 4; ++i) { 
     4461      int m = SVOp->getMaskElt(i); 
     4462      unsigned mm = m >= 0 ? (unsigned) m : i; 
     4463      idx |= mm << (3-i)*3; 
     4464    } 
     4465 
     4466    SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, VT, 
     4467                             DAG.getConstant(idx, MVT::i32)); 
     4468    return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3); 
     4469  } 
     4470 
    42584471  // Cases that are handled by instructions that take permute immediates 
    42594472  // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 
    42604473  // selected by the instruction selector. 
     
    56255838        return std::make_pair(0U, &PPC::F4RCRegClass); 
    56265839      if (VT == MVT::f64) 
    56275840        return std::make_pair(0U, &PPC::F8RCRegClass); 
     5841      if (VT == MVT::v2f64 && PPCSubTarget.hasFP2()) 
     5842        return std::make_pair(0U, &PPC::DFRCRegClass); 
     5843      if (VT == MVT::v4f64 && PPCSubTarget.hasQPX()) 
     5844        return std::make_pair(0U, &PPC::QFRCRegClass); 
    56285845      break; 
    56295846    case 'v': 
    56305847      return std::make_pair(0U, &PPC::VRRCRegClass); 
     
    57555972  return false; 
    57565973} 
    57575974 
     5975bool PPCTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT) const { 
     5976  return true; 
     5977} 
     5978 
    57585979SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 
    57595980                                           SelectionDAG &DAG) const { 
    57605981  MachineFunction &MF = DAG.getMachineFunction(); 
  • lib/Target/PowerPC/PPCISelLowering.h

    diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
    index 83fecaa..b728598 100644
    a b  
    174174      ///   operand #3 optional in flag 
    175175      TC_RETURN, 
    176176 
     177      /// QVFPERM = This corresponds to the QPX qvfperm instruction. 
     178      QVFPERM, 
     179 
     180      /// QVGPCI = This corresponds to the QPX qvgpci instruction. 
     181      QVGPCI, 
     182 
     183      /// QVALIGNI = This corresponds to the QPX qvaligni instruction. 
     184      QVALIGNI, 
     185 
     186      /// QVESPLATI = This corresponds to the QPX qvesplati instruction. 
     187      QVESPLATI, 
     188 
    177189      /// STD_32 - This is the STD instruction for use with "32-bit" registers. 
    178190      STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE, 
    179191 
     
    233245    /// size, return the constant being splatted.  The ByteSize field indicates 
    234246    /// the number of bytes of each element [124] -> [bhw]. 
    235247    SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 
     248 
     249    /// qvaligni - If this is a qvaligni shuffle mask, return the shift 
     250    /// amount, otherwise return -1. 
     251    int isQVALIGNIShuffleMask(SDNode *N); 
    236252  } 
    237253 
    238254  class PPCTargetLowering : public TargetLowering { 
     
    349365 
    350366    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 
    351367 
     368    virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT) const; 
     369 
    352370    /// getOptimalMemOpType - Returns the target specific optimal type for load 
    353371    /// and store operations as a result of memset, memcpy, and memmove 
    354372    /// lowering. If DstAlign is zero that means it's safe to destination 
  • lib/Target/PowerPC/PPCInstr64Bit.td

    diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
    index 920fa1a..4eaa93c 100644
    a b  
    6464                    PPC970_Unit_BRU; 
    6565 
    6666// Darwin ABI Calls. 
    67 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 
     67let isCall = 1, PPC970_Unit = 7, 
     68  Defs = [LR8, 
     69          F0_ext,F1_ext,F2_ext,F3_ext,F4_ext,F5_ext,F6_ext,F7_ext,F8_ext,F9_ext, 
     70          F10_ext,F11_ext,F12_ext,F13_ext,F14_ext,F15_ext,F16_ext,F17_ext,F18_ext,F19_ext, 
     71          F20_ext,F21_ext,F22_ext,F23_ext,F24_ext,F25_ext,F26_ext,F27_ext,F28_ext,F29_ext, 
     72          F30_ext,F31_ext] in { 
    6873  // Convenient aliases for call instructions 
    6974  let Uses = [RM] in { 
    7075    def BL8_Darwin  : IForm<18, 0, 1, 
     
    8489 
    8590// ELF 64 ABI Calls = Darwin ABI Calls 
    8691// Used to define BL8_ELF and BLA8_ELF 
    87 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 
     92let isCall = 1, PPC970_Unit = 7, 
     93  Defs = [LR8, 
     94          F0_ext,F1_ext,F2_ext,F3_ext,F4_ext,F5_ext,F6_ext,F7_ext,F8_ext,F9_ext, 
     95          F10_ext,F11_ext,F12_ext,F13_ext,F14_ext,F15_ext,F16_ext,F17_ext,F18_ext,F19_ext, 
     96          F20_ext,F21_ext,F22_ext,F23_ext,F24_ext,F25_ext,F26_ext,F27_ext,F28_ext,F29_ext, 
     97          F30_ext,F31_ext] in { 
    8898  // Convenient aliases for call instructions 
    8999  let Uses = [RM] in { 
    90100    def BL8_ELF  : IForm<18, 0, 1, 
  • (a) /dev/null vs. (b) b/lib/Target/PowerPC/PPCInstrFP2.td

    diff --git a/lib/Target/PowerPC/PPCInstrFP2.td b/lib/Target/PowerPC/PPCInstrFP2.td
    new file mode 100644
    index 0000000..4bb069a
    a b  
     1//===- PPCInstrFP2.td - The PowerPC FP2 (Double Hummer) Extension --*- tablegen -*-===// 
     2//  
     3//                     The LLVM Compiler Infrastructure 
     4// 
     5// This file is distributed under the University of Illinois Open Source 
     6// License. See LICENSE.TXT for details. 
     7//  
     8//===----------------------------------------------------------------------===// 
     9// 
     10// This file describes the FP2 (Double Hummer) extension to the PowerPC instruction set. 
     11// Reference: 
     12// PPC440 FP2 Architecture. IBM (as updated in) 2011. 
     13// Available from: https://wiki.alcf.anl.gov/index.php/References 
     14// 
     15//===----------------------------------------------------------------------===// 
     16 
     17//===----------------------------------------------------------------------===// 
     18// Helpers for defining instructions that directly correspond to intrinsics. 
     19 
     20// FP2A1_Int - A AForm_1 intrinsic definition. 
     21class FP2A1_Int<bits<6> opcode, bits<5> xo, string opc, Intrinsic IntID> 
     22  : AForm_1<opcode, xo, (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRB, DFRC:$FRC), 
     23              !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), FPGeneral, 
     24                       [(set DFRC:$FRT, (IntID DFRC:$FRA, DFRC:$FRB, DFRC:$FRC))]>; 
     25// FP2A3_Int - A AForm_3 intrinsic definition. 
     26class FP2A3_Int<bits<6> opcode, bits<5> xo, string opc, Intrinsic IntID> 
     27  : AForm_3<opcode, xo, (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRC), 
     28              !strconcat(opc, " $FRT, $FRA, $FRC"), FPGeneral, 
     29                       [(set DFRC:$FRT, (IntID DFRC:$FRA, DFRC:$FRC))]>; 
     30// FP2A4_Int - A AForm_4 intrinsic definition. 
     31class FP2A4_Int<bits<6> opcode, bits<5> xo, string opc, Intrinsic IntID> 
     32  : AForm_4<opcode, xo, (outs DFRC:$FRT), (ins DFRC:$FRB), 
     33              !strconcat(opc, " $FRT, $FRB"), FPGeneral, 
     34                       [(set DFRC:$FRT, (IntID DFRC:$FRB))]>; 
     35// FP2X18_Int - A XForm_18 intrinsic definition. 
     36class FP2X18_Int<bits<6> opcode, bits<10> xo, string opc, Intrinsic IntID> 
     37  : XForm_18<opcode, xo, (outs DFRC:$FRT), (ins DFRC:$FRB), 
     38              !strconcat(opc, " $FRT, $FRB"), FPGeneral, 
     39                       [(set DFRC:$FRT, (IntID DFRC:$FRB))]>; 
     40// FP2X19_Int - A XForm_19 intrinsic definition. 
     41class FP2X19_Int<bits<6> opcode, bits<10> xo, string opc, Intrinsic IntID> 
     42  : XForm_19<opcode, xo, (outs DFRC:$FRT), (ins DFRC:$FRB), 
     43              !strconcat(opc, " $FRT, $FRB"), FPGeneral, 
     44                       [(set DFRC:$FRT, (IntID DFRC:$FRB))]>; 
     45 
     46//===----------------------------------------------------------------------===// 
     47// Pattern Frags. 
     48 
     49def extloadv2f32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 
     50  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v2f32; 
     51}]>; 
     52 
     53def truncstorev2f32 : PatFrag<(ops node:$val, node:$ptr), 
     54                            (truncstore node:$val, node:$ptr), [{ 
     55  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v2f32; 
     56}]>; 
     57 
     58def vector_shuffle_0_0 : PatFrag<(ops node:$lhs, node:$rhs), 
     59                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     60  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     61  return SV->getMaskElt(0) == 0 && SV->getMaskElt(1) == 0; 
     62}]>; 
     63 
     64def vector_shuffle_1_1 : PatFrag<(ops node:$lhs, node:$rhs), 
     65                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     66  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     67  return SV->getMaskElt(0) == 1 && SV->getMaskElt(1) == 1; 
     68}]>; 
     69 
     70def vector_shuffle_1_0 : PatFrag<(ops node:$lhs, node:$rhs), 
     71                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     72  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     73  return SV->getMaskElt(0) == 1 && SV->getMaskElt(1) == 0; 
     74}]>; 
     75 
     76def vector_shuffle_1_u : PatFrag<(ops node:$lhs, node:$rhs), 
     77                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     78  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     79  return SV->getMaskElt(0) == 1 && SV->getMaskElt(1) < 0; 
     80}]>; 
     81 
     82def vector_shuffle_0_2 : PatFrag<(ops node:$lhs, node:$rhs), 
     83                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     84  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     85  return SV->getMaskElt(0) == 0 && SV->getMaskElt(1) == 2; 
     86}]>; 
     87 
     88def vector_shuffle_2_0 : PatFrag<(ops node:$lhs, node:$rhs), 
     89                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     90  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     91  return SV->getMaskElt(0) == 2 && SV->getMaskElt(1) == 0; 
     92}]>; 
     93 
     94def vector_shuffle_0_3 : PatFrag<(ops node:$lhs, node:$rhs), 
     95                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     96  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     97  return SV->getMaskElt(0) == 0 && SV->getMaskElt(1) == 3; 
     98}]>; 
     99 
     100def vector_shuffle_3_0 : PatFrag<(ops node:$lhs, node:$rhs), 
     101                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     102  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     103  return SV->getMaskElt(0) == 3 && SV->getMaskElt(1) == 0; 
     104}]>; 
     105 
     106def vector_shuffle_1_2 : PatFrag<(ops node:$lhs, node:$rhs), 
     107                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     108  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     109  return SV->getMaskElt(0) == 1 && SV->getMaskElt(1) == 2; 
     110}]>; 
     111 
     112def vector_shuffle_2_1 : PatFrag<(ops node:$lhs, node:$rhs), 
     113                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     114  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     115  return SV->getMaskElt(0) == 2 && SV->getMaskElt(1) == 1; 
     116}]>; 
     117 
     118def vector_shuffle_1_3 : PatFrag<(ops node:$lhs, node:$rhs), 
     119                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     120  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     121  return SV->getMaskElt(0) == 1 && SV->getMaskElt(1) == 3; 
     122}]>; 
     123 
     124def vector_shuffle_3_1 : PatFrag<(ops node:$lhs, node:$rhs), 
     125                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     126  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     127  return SV->getMaskElt(0) == 3 && SV->getMaskElt(1) == 1; 
     128}]>; 
     129 
     130def build_vector_1_neg1 : PatLeaf<(build_vector), [{ 
     131  if (N->getNumOperands() < 2) return false; 
     132  SDValue v1 = N->getOperand(0); 
     133  SDValue v2 = N->getOperand(1); 
     134 
     135  if (isa<ConstantSDNode>(v1)) { 
     136    if (cast<ConstantSDNode>(v1)->getAPIntValue() != 1) 
     137      return false; 
     138  } else if (isa<ConstantFPSDNode>(v1)) { 
     139    if (!cast<ConstantFPSDNode>(v1)->isExactlyValue(1.0)) 
     140      return false; 
     141  } else return false; 
     142 
     143  if (isa<ConstantSDNode>(v2)) { 
     144    if (-cast<ConstantSDNode>(v2)->getAPIntValue() != 1) 
     145      return false; 
     146  } else if (isa<ConstantFPSDNode>(v2)) { 
     147    if (!cast<ConstantFPSDNode>(v2)->isExactlyValue(-1.0)) 
     148      return false; 
     149  } else return false; 
     150 
     151  return true; 
     152}]>; 
     153 
     154def build_vector_neg1_1 : PatLeaf<(build_vector), [{ 
     155  if (N->getNumOperands() < 2) return false; 
     156  SDValue v1 = N->getOperand(0); 
     157  SDValue v2 = N->getOperand(1); 
     158 
     159  if (isa<ConstantSDNode>(v1)) { 
     160    if (-cast<ConstantSDNode>(v1)->getAPIntValue() != 1) 
     161      return false; 
     162  } else if (isa<ConstantFPSDNode>(v1)) { 
     163    if (!cast<ConstantFPSDNode>(v1)->isExactlyValue(-1.0)) 
     164      return false; 
     165  } else return false; 
     166 
     167  if (isa<ConstantSDNode>(v2)) { 
     168    if (cast<ConstantSDNode>(v2)->getAPIntValue() != 1) 
     169      return false; 
     170  } else if (isa<ConstantFPSDNode>(v2)) { 
     171    if (!cast<ConstantFPSDNode>(v2)->isExactlyValue(1.0)) 
     172      return false; 
     173  } else return false; 
     174 
     175  return true; 
     176}]>; 
     177 
     178//===----------------------------------------------------------------------===// 
     179// Instruction Definitions. 
     180 
     181let Uses = [RM] in { 
     182  // Add Instructions 
     183  let isCommutable = 1 in { 
     184    def FPADD : AForm_2<0, 12, 
     185                        (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRB), 
     186                        "fpadd $FRT, $FRA, $FRB", FPGeneral, 
     187                        [(set DFRC:$FRT, (fadd DFRC:$FRA, DFRC:$FRB))]>; 
     188    } 
     189  def FPSUB : AForm_2<0, 13, 
     190                      (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRB), 
     191                      "fpsub $FRT, $FRA, $FRB", FPGeneral, 
     192                      [(set DFRC:$FRT, (fsub DFRC:$FRA, DFRC:$FRB))]>; 
     193 
     194  // Estimate Instructions 
     195  def FPRE : FP2A4_Int<0, 14, "fpre", int_ppc_fp2_fpre>; 
     196  def FPRSQRTE : FP2A4_Int<0, 15, "fprsqrte", int_ppc_fp2_fpre>; 
     197 
     198  // Multiply Instructions 
     199  let isCommutable = 1 in { 
     200    def FPMUL : AForm_3<0, 8, 
     201                        (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRB), 
     202                        "fpmul $FRT, $FRA, $FRB", FPGeneral, 
     203                        [(set DFRC:$FRT, (fmul DFRC:$FRA, DFRC:$FRB))]>; 
     204  } 
     205  def FXMUL : FP2A3_Int<0, 9, "fxmul", int_ppc_fp2_fxmul>; 
     206  def FXPMUL : FP2A3_Int<0, 10, "fxpmul", int_ppc_fp2_fxpmul>; 
     207  def FXSMUL : FP2A3_Int<0, 11, "fxsmul", int_ppc_fp2_fxsmul>; 
     208 
     209  // Multiply-add instructions 
     210  def FPMADD : AForm_1<0, 16, 
     211                      (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRB, DFRC:$FRC), 
     212                      "fpmadd $FRT, $FRA, $FRC, $FRB", FPGeneral, 
     213                      [(set DFRC:$FRT, (fadd (fmul DFRC:$FRA, DFRC:$FRC), 
     214                                             DFRC:$FRB))]>, 
     215                      Requires<[FPContractions]>; 
     216  def FPNMADD : AForm_1<0, 20, 
     217                      (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRB, DFRC:$FRC), 
     218                      "fpnmadd $FRT, $FRA, $FRC, $FRB", FPGeneral, 
     219                      [(set DFRC:$FRT, (fneg (fadd (fmul DFRC:$FRA, DFRC:$FRC), 
     220                                             DFRC:$FRB)))]>, 
     221                      Requires<[FPContractions]>; 
     222  def FPMSUB : AForm_1<0, 24, 
     223                      (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRB, DFRC:$FRC), 
     224                      "fpmsub $FRT, $FRA, $FRC, $FRB", FPGeneral, 
     225                      [(set DFRC:$FRT, (fsub (fmul DFRC:$FRA, DFRC:$FRC), 
     226                                             DFRC:$FRB))]>, 
     227                      Requires<[FPContractions]>; 
     228  def FPNMSUB : AForm_1<0, 28, 
     229                      (outs DFRC:$FRT), (ins DFRC:$FRA, DFRC:$FRB, DFRC:$FRC), 
     230                      "fpnmsub $FRT, $FRA, $FRC, $FRB", FPGeneral, 
     231                      [(set DFRC:$FRT, (fneg (fsub (fmul DFRC:$FRA, DFRC:$FRC), 
     232                                             DFRC:$FRB)))]>, 
     233                      Requires<[FPContractions]>; 
     234  def FXMADD : FP2A1_Int<0, 17, "fxmadd", int_ppc_fp2_fxmadd>; 
     235  def FXNMADD : FP2A1_Int<0, 21, "fxnmadd", int_ppc_fp2_fxnmadd>; 
     236  def FXMSUB : FP2A1_Int<0, 25, "fxmsub", int_ppc_fp2_fxmsub>; 
     237  def FXNMSUB : FP2A1_Int<0, 29, "fxnmsub", int_ppc_fp2_fxnmsub>; 
     238  def FXCPMADD : FP2A1_Int<0, 18, "fxcpmadd", int_ppc_fp2_fxcpmadd>; 
     239  def FXCSMADD : FP2A1_Int<0, 19, "fxcsmadd", int_ppc_fp2_fxcsmadd>; 
     240  def FXCPNMADD : FP2A1_Int<0, 22, "fxcpnmadd", int_ppc_fp2_fxcpnmadd>; 
     241  def FXCSNMADD : FP2A1_Int<0, 23, "fxcsnmadd", int_ppc_fp2_fxcsnmadd>; 
     242  def FXCPMSUB : FP2A1_Int<0, 26, "fxcpmsub", int_ppc_fp2_fxcpmsub>; 
     243  def FXCSMSUB : FP2A1_Int<0, 27, "fxcsmsub", int_ppc_fp2_fxcsmsub>; 
     244  def FXCPNMSUB : FP2A1_Int<0, 30, "fxcpnmsub", int_ppc_fp2_fxcpnmsub>; 
     245  def FXCSNMSUB : FP2A1_Int<0, 31, "fxcsnmsub", int_ppc_fp2_fxcsnmsub>; 
     246 
     247  // Asymmetric multiply-add instructions 
     248  def FXCPNPMA : FP2A1_Int<4, 24, "fxcpnpma", int_ppc_fp2_fxcpnpma>; 
     249  def FXCSNPMA : FP2A1_Int<4, 25, "fxcsnpma", int_ppc_fp2_fxcsnpma>; 
     250  def FXCPNSMA : FP2A1_Int<4, 26, "fxcpnsma", int_ppc_fp2_fxcpnsma>; 
     251  def FXCSNSMA : FP2A1_Int<4, 27, "fxcsnsma", int_ppc_fp2_fxcsnsma>; 
     252 
     253  // Complex multiply-add instructions 
     254  def FXCXNPMA : FP2A1_Int<4, 29, "fxcxnpma", int_ppc_fp2_fxcxnpma>; 
     255  def FXCXNSMA : FP2A1_Int<4, 30, "fxcxnsma", int_ppc_fp2_fxcxnsma>; 
     256  def FXCXMA : FP2A1_Int<4, 28, "fxcxma", int_ppc_fp2_fxcxma>; 
     257  def FXCXNMS : FP2A1_Int<4, 31, "fxcxnms", int_ppc_fp2_fxcxnms>; 
     258 
     259  // Select Instruction 
     260  def FPSEL : FP2A1_Int<0, 5, "fpsel", int_ppc_fp2_fpsel>; 
     261 
     262  // Convert and Round Instructions 
     263  def FPCTIW : FP2X19_Int<0, 576, "fpctiw", int_ppc_fp2_fpctiw>; 
     264  def FPCTIWZ : FP2X19_Int<0, 704, "fpctiwz", int_ppc_fp2_fpctiwz>; 
     265  def FPRSP : FP2X19_Int<0, 192, "fprsp", int_ppc_fp2_fprsp>; 
     266 
     267  // Move Instructions 
     268  def FPMR : XForm_19<0, 32, 
     269                      (outs DFRC:$FRT), (ins DFRC:$FRB), 
     270                      "fpmr $FRT, $FRB", FPGeneral, 
     271                      [/* (set DFRC:$FRT, DFRC:$FRB) */]>; 
     272  def FPNEG : XForm_19<0, 160, 
     273                      (outs DFRC:$FRT), (ins DFRC:$FRB), 
     274                      "fpneg $FRT, $FRB", FPGeneral, 
     275                      [(set DFRC:$FRT, (fneg DFRC:$FRB))]>; 
     276  def FPABS : XForm_19<0, 96, 
     277                      (outs DFRC:$FRT), (ins DFRC:$FRB), 
     278                      "fpabs $FRT, $FRB", FPGeneral, 
     279                      [(set DFRC:$FRT, (fabs DFRC:$FRB))]>; 
     280  def FPNABS : XForm_19<0, 224, 
     281                      (outs DFRC:$FRT), (ins DFRC:$FRB), 
     282                      "fpnabs $FRT, $FRB", FPGeneral, 
     283                      [(set DFRC:$FRT, (fneg (fabs DFRC:$FRB)))]>; 
     284  let Constraints = "$FRTi = $FRT" in { 
     285    def FSMR : XForm_19<0, 288, 
     286                        (outs DFRC:$FRT), (ins DFRC:$FRTi, DFRC:$FRB), 
     287                        "fsmr $FRT, $FRB", FPGeneral, []>; 
     288    def FSNEG : XForm_19<0, 416, 
     289                        (outs DFRC:$FRT), (ins DFRC:$FRTi, DFRC:$FRB), 
     290                        "fsneg $FRT, $FRB", FPGeneral, []>; 
     291    def FSABS : XForm_19<0, 352, 
     292                        (outs DFRC:$FRT), (ins DFRC:$FRTi, DFRC:$FRB), 
     293                        "fsabs $FRT, $FRB", FPGeneral, []>; 
     294    def FSNABS : XForm_19<0, 480, 
     295                        (outs DFRC:$FRT), (ins DFRC:$FRTi, DFRC:$FRB), 
     296                        "fsnabs $FRT, $FRB", FPGeneral, []>; 
     297  } 
     298  def FXMR : XForm_19<0, 544, 
     299                      (outs DFRC:$FRT), (ins DFRC:$FRB), 
     300                      "fxmr $FRT, $FRB", FPGeneral, 
     301                      [(set DFRC:$FRT, (vector_shuffle_1_0 DFRC:$FRB, undef))]>; 
     302  let Constraints = "$FRTi = $FRT" in { 
     303    def FSMFP : XForm_19<0, 928, 
     304                        (outs DFRC:$FRT), (ins DFRC:$FRTi, DFRC:$FRB), 
     305                        "fsmfp $FRT, $FRB", FPGeneral, []>; 
     306    def FSMTP : XForm_19<0, 800, 
     307                        (outs DFRC:$FRT), (ins DFRC:$FRTi, DFRC:$FRB), 
     308                        "fsmtp $FRT, $FRB", FPGeneral, []>; 
     309  } 
     310 
     311  // Compare Instruction 
     312  def FSCMP : XForm_17<0, 320, 
     313                      (outs CRRC:$crD), (ins DFRC:$FRA, DFRC:$FRB), 
     314                      "fscmp $crD, $FRA, $FRB", FPCompare>; 
     315 
     316  // Load indexed instructions 
     317  let canFoldAsLoad = 1 in { 
     318    def LFPDX : XForm_1<31, 462, 
     319                        (outs DFRC:$FRT), (ins memrr:$src), 
     320                        "lfpdx $FRT, $src", LdStLoad, 
     321                        [(set DFRC:$FRT, (load xoaddr:$src))]>; 
     322    def LFPDUX : XForm_1<31, 494, 
     323                        (outs DFRC:$FRT), (ins memrr:$src), 
     324                        "lfpdux $FRT, $src", LdStLoad, []>; 
     325    def LFPSX : XForm_1<31, 398, 
     326                        (outs DFRC:$FRT), (ins memrr:$src), 
     327                        "lfpsx $FRT, $src", LdStLoad, 
     328                        [(set DFRC:$FRT, (extloadv2f32 xoaddr:$src))]>; 
     329    def LFPSUX : XForm_1<31, 430, 
     330                        (outs DFRC:$FRT), (ins memrr:$src), 
     331                        "lfpsux $FRT, $src", LdStLoad, []>; 
     332    let Constraints = "$FRTi = $FRT" in { 
     333      def LFSDX : XForm_1<31, 206, 
     334                          (outs DFRC:$FRT), (ins DFRC:$FRTi, memrr:$src), 
     335                          "lfsdx $FRT, $src", LdStLoad, []>; 
     336      def LFSDUX : XForm_1<31, 238, 
     337                          (outs DFRC:$FRT), (ins DFRC:$FRTi, memrr:$src), 
     338                          "lfsdux $FRT, $src", LdStLoad, []>; 
     339      def LFSSX : XForm_1<31, 142, 
     340                          (outs DFRC:$FRT), (ins DFRC:$FRTi, memrr:$src), 
     341                          "lfssx $FRT, $src", LdStLoad, []>; 
     342      def LFSSUX : XForm_1<31, 174, 
     343                          (outs DFRC:$FRT), (ins DFRC:$FRTi, memrr:$src), 
     344                          "lfssux $FRT, $src", LdStLoad, []>; 
     345    } 
     346    def LFXDX : XForm_1<31, 334, 
     347                        (outs DFRC:$FRT), (ins memrr:$src), 
     348                        "lfxdx $FRT, $src", LdStLoad, 
     349                        [(set DFRC:$FRT, (vector_shuffle_1_0 (load xoaddr:$src), undef))]>; 
     350    def LFXDUX : XForm_1<31, 366, 
     351                        (outs DFRC:$FRT), (ins memrr:$src), 
     352                        "lfxdux $FRT, $src", LdStLoad, []>; 
     353    def LFXSX : XForm_1<31, 270, 
     354                        (outs DFRC:$FRT), (ins memrr:$src), 
     355                        "lfxsx $FRT, $src", LdStLoad, 
     356                        [(set DFRC:$FRT, (vector_shuffle_1_0 (extloadv2f32 xoaddr:$src), undef))]>; 
     357    def LFXSUX : XForm_1<31, 302, 
     358                        (outs DFRC:$FRT), (ins memrr:$src), 
     359                        "lfxsux $FRT, $src", LdStLoad, []>; 
     360  } 
     361 
     362  // Store indexed instructions 
     363  def STFPDX : XForm_8<31, 974, 
     364                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     365                      "stfpdx $FRT, $dst", LdStStore, 
     366                      [(store DFRC:$FRT, xoaddr:$dst)]>; 
     367  def STFPDUX : XForm_8<31, 1006, 
     368                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     369                      "stfpdux $FRT, $dst", LdStStore, []>; 
     370  def STFPSX : XForm_8<31, 910, 
     371                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     372                      "stfpsx $FRT, $dst", LdStStore, 
     373                      [(truncstorev2f32 DFRC:$FRT, xoaddr:$dst)]>; 
     374  def STFPSUX : XForm_8<31, 942, 
     375                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     376                      "stfpsux $FRT, $dst", LdStStore, []>; 
     377  def STFPIWX : XForm_8<31, 526, 
     378                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     379                      "stfpiwx $FRT, $dst", LdStStore, 
     380                      [/* (store DFRC:$FRT, xoaddr:$dst) */]>; 
     381  def STFSDX : XForm_8<31, 718, 
     382                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     383                      "stfpdx $FRT, $dst", LdStStore, 
     384                      [(store (f64 (vector_extract DFRC:$FRT, 1)), xoaddr:$dst)]>; 
     385  def STFSDUX : XForm_8<31, 750, 
     386                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     387                      "stfpdux $FRT, $dst", LdStStore, []>; 
     388  def STFSSX : XForm_8<31, 654, 
     389                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     390                      "stfssx $FRT, $dst", LdStStore, 
     391                      [(truncstoref32 (f64 (vector_extract DFRC:$FRT, 1)), xoaddr:$dst)]>; 
     392  def STFSSUX : XForm_8<31, 654, 
     393                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     394                      "stfssux $FRT, $dst", LdStStore, []>; 
     395  def STFXDX : XForm_8<31, 846, 
     396                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     397                      "stfxdx $FRT, $dst", LdStStore, 
     398                      [(store (vector_shuffle_1_0 DFRC:$FRT, undef), xoaddr:$dst)]>; 
     399  def STFXDUX : XForm_8<31, 878, 
     400                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     401                      "stfxdux $FRT, $dst", LdStStore, []>; 
     402  def STFXSX : XForm_8<31, 782, 
     403                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     404                      "stfxsx $FRT, $dst", LdStStore, 
     405                      [(truncstorev2f32 (vector_shuffle_1_0 DFRC:$FRT, undef), xoaddr:$dst)]>; 
     406  def STFXSUX : XForm_8<31, 814, 
     407                      (outs), (ins DFRC:$FRT, memrr:$dst), 
     408                      "stfxsux $FRT, $dst", LdStStore, []>; 
     409} 
     410 
     411//===----------------------------------------------------------------------===// 
     412// Additional FP2 (Double Hummer) Patterns 
     413// 
     414 
     415def : Pat<(v2f64 (scalar_to_vector F8RC:$A)), 
     416          (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), F8RC:$A, sub_64)>; 
     417 
     418def : Pat<(f64 (vector_extract DFRC:$S, 0)), 
     419          (EXTRACT_SUBREG DFRC:$S, sub_64)>; 
     420 
     421def : Pat<(f64 (vector_extract DFRC:$S, 1)), 
     422          (EXTRACT_SUBREG (FXMR DFRC:$S), sub_64)>; 
     423 
     424def : Pat<(vector_shuffle_0_0 DFRC:$A, undef), 
     425          (FSMFP DFRC:$A, DFRC:$A)>; 
     426 
     427def : Pat<(vector_shuffle_1_1 DFRC:$A, undef), 
     428          (FSMTP DFRC:$A, DFRC:$A)>; 
     429 
     430def : Pat<(vector_shuffle_1_u DFRC:$A, undef), 
     431          (FSMTP DFRC:$A, DFRC:$A)>; 
     432 
     433def : Pat<(vector_shuffle_0_2 DFRC:$A, DFRC:$B), 
     434          (FSMFP DFRC:$A, DFRC:$B)>; 
     435 
     436def : Pat<(vector_shuffle_2_0 DFRC:$A, DFRC:$B), 
     437          (FSMFP DFRC:$B, DFRC:$A)>; 
     438 
     439def : Pat<(vector_shuffle_0_3 DFRC:$A, DFRC:$B), 
     440          (FSMR DFRC:$A, DFRC:$B)>; 
     441 
     442def : Pat<(vector_shuffle_3_0 DFRC:$A, DFRC:$B), 
     443          (FXMR (FSMR DFRC:$A, DFRC:$B))>; 
     444 
     445def : Pat<(vector_shuffle_1_2 DFRC:$A, DFRC:$B), 
     446          (FXMR (FSMR DFRC:$B, DFRC:$A))>; 
     447 
     448def : Pat<(vector_shuffle_2_1 DFRC:$A, DFRC:$B), 
     449          (FSMR DFRC:$B, DFRC:$A)>; 
     450 
     451def : Pat<(vector_shuffle_1_3 DFRC:$A, DFRC:$B), 
     452          (FSMR (FXMR DFRC:$A), DFRC:$B)>; 
     453 
     454def : Pat<(vector_shuffle_3_1 DFRC:$A, DFRC:$B), 
     455          (FSMR (FXMR DFRC:$B), DFRC:$A)>; 
     456 
     457// Add Instructions 
     458def : Pat<(int_ppc_fp2_fpadd DFRC:$A, DFRC:$B), 
     459          (FPADD DFRC:$A, DFRC:$B)>; 
     460def : Pat<(int_ppc_fp2_fpsub DFRC:$A, DFRC:$B), 
     461          (FPSUB DFRC:$A, DFRC:$B)>; 
     462 
     463// Multiply Instructions 
     464def : Pat<(int_ppc_fp2_fpmul DFRC:$A, DFRC:$B), 
     465          (FPMUL DFRC:$A, DFRC:$B)>; 
     466 
     467def : Pat<(fmul (vector_shuffle_1_0 DFRC:$A, undef), DFRC:$B), 
     468          (FXMUL DFRC:$A, DFRC:$B)>; 
     469 
     470def : Pat<(fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$B), 
     471          (FXPMUL DFRC:$A, DFRC:$B)>; 
     472 
     473def : Pat<(fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$B), 
     474          (FXSMUL DFRC:$A, DFRC:$B)>; 
     475 
     476// Multiply-add instructions 
     477def : Pat<(int_ppc_fp2_fpmadd DFRC:$A, DFRC:$B, DFRC:$C), 
     478          (FPMADD DFRC:$A, DFRC:$B, DFRC:$C)>; 
     479def : Pat<(int_ppc_fp2_fpnmadd DFRC:$A, DFRC:$B, DFRC:$C), 
     480          (FPNMADD DFRC:$A, DFRC:$B, DFRC:$C)>; 
     481def : Pat<(int_ppc_fp2_fpmsub DFRC:$A, DFRC:$B, DFRC:$C), 
     482          (FPMSUB DFRC:$A, DFRC:$B, DFRC:$C)>; 
     483def : Pat<(int_ppc_fp2_fpnmsub DFRC:$A, DFRC:$B, DFRC:$C), 
     484          (FPNMSUB DFRC:$A, DFRC:$B, DFRC:$C)>; 
     485 
     486def : Pat<(fadd (fmul (vector_shuffle_1_0 DFRC:$A, undef), DFRC:$C), DFRC:$B), 
     487          (FXMADD DFRC:$A, DFRC:$B, DFRC:$C)>; 
     488 
     489def : Pat<(fneg (fadd (fmul (vector_shuffle_1_0 DFRC:$A, undef), DFRC:$C), DFRC:$B)), 
     490          (FXNMADD DFRC:$A, DFRC:$B, DFRC:$C)>; 
     491 
     492def : Pat<(fsub (fmul (vector_shuffle_1_0 DFRC:$A, undef), DFRC:$C), DFRC:$B), 
     493          (FXMSUB DFRC:$A, DFRC:$B, DFRC:$C)>; 
     494 
     495def : Pat<(fneg (fsub (fmul (vector_shuffle_1_0 DFRC:$A, undef), DFRC:$C), DFRC:$B)), 
     496          (FXNMSUB DFRC:$A, DFRC:$B, DFRC:$C)>; 
     497 
     498def : Pat<(fadd (fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$C), DFRC:$B), 
     499          (FXCPMADD DFRC:$A, DFRC:$B, DFRC:$C)>; 
     500 
     501def : Pat<(fadd (fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$C), DFRC:$B), 
     502          (FXCSMADD DFRC:$A, DFRC:$B, DFRC:$C)>; 
     503 
     504def : Pat<(fneg (fadd (fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$C), DFRC:$B)), 
     505          (FXCPNMADD DFRC:$A, DFRC:$B, DFRC:$C)>; 
     506 
     507def : Pat<(fneg (fadd (fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$C), DFRC:$B)), 
     508          (FXCSNMADD DFRC:$A, DFRC:$B, DFRC:$C)>; 
     509 
     510def : Pat<(fsub (fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$C), DFRC:$B), 
     511          (FXCPMSUB DFRC:$A, DFRC:$B, DFRC:$C)>; 
     512 
     513def : Pat<(fsub (fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$C), DFRC:$B), 
     514          (FXCSMSUB DFRC:$A, DFRC:$B, DFRC:$C)>; 
     515 
     516def : Pat<(fneg (fsub (fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$C), DFRC:$B)), 
     517          (FXCPNMSUB DFRC:$A, DFRC:$B, DFRC:$C)>; 
     518 
     519def : Pat<(fneg (fsub (fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$C), DFRC:$B)), 
     520          (FXCSNMSUB DFRC:$A, DFRC:$B, DFRC:$C)>; 
     521 
     522// Asymmetric multiply-add instructions 
     523def : Pat<(fmul (fadd (fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$C), 
     524            (fmul DFRC:$B, (v2f64 build_vector_neg1_1))), (v2f64 build_vector_neg1_1)), 
     525          (FXCPNPMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     526def : Pat<(fmul (fsub (fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$C), 
     527            (fmul DFRC:$B, (v2f64 build_vector_1_neg1))), (v2f64 build_vector_neg1_1)), 
     528          (FXCPNPMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     529 
     530def : Pat<(fmul (fadd (fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$C), 
     531            (fmul DFRC:$B, (v2f64 build_vector_neg1_1))), (v2f64 build_vector_neg1_1)), 
     532          (FXCSNPMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     533def : Pat<(fmul (fsub (fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$C), 
     534            (fmul DFRC:$B, (v2f64 build_vector_1_neg1))), (v2f64 build_vector_neg1_1)), 
     535          (FXCSNPMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     536 
     537def : Pat<(fmul (fadd (fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$C), 
     538            (fmul DFRC:$B, (v2f64 build_vector_1_neg1))), (v2f64 build_vector_1_neg1)), 
     539          (FXCPNSMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     540def : Pat<(fmul (fsub (fmul (vector_shuffle_0_0 DFRC:$A, undef), DFRC:$C), 
     541            (fmul DFRC:$B, (v2f64 build_vector_neg1_1))), (v2f64 build_vector_1_neg1)), 
     542          (FXCPNSMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     543 
     544def : Pat<(fmul (fadd (fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$C), 
     545            (fmul DFRC:$B, (v2f64 build_vector_1_neg1))), (v2f64 build_vector_1_neg1)), 
     546          (FXCSNSMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     547def : Pat<(fmul (fsub (fmul (vector_shuffle_1_1 DFRC:$A, undef), DFRC:$C), 
     548            (fmul DFRC:$B, (v2f64 build_vector_neg1_1))), (v2f64 build_vector_1_neg1)), 
     549          (FXCSNSMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     550 
     551// Complex multiply-add instructions 
     552def : Pat<(fmul (fadd (fmul (vector_shuffle_1_1 DFRC:$A, undef), 
     553                            (vector_shuffle_1_0 DFRC:$C, undef)), 
     554            (fmul DFRC:$B, (v2f64 build_vector_neg1_1))), (v2f64 build_vector_neg1_1)), 
     555          (FXCXNPMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     556def : Pat<(fmul (fsub (fmul (vector_shuffle_1_1 DFRC:$A, undef), 
     557                            (vector_shuffle_1_0 DFRC:$C, undef)), 
     558            (fmul DFRC:$B, (v2f64 build_vector_1_neg1))), (v2f64 build_vector_neg1_1)), 
     559          (FXCXNPMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     560 
     561def : Pat<(fmul (fadd (fmul (vector_shuffle_1_1 DFRC:$A, undef), 
     562                            (vector_shuffle_1_0 DFRC:$C, undef)), 
     563            (fmul DFRC:$B, (v2f64 build_vector_1_neg1))), (v2f64 build_vector_1_neg1)), 
     564          (FXCXNSMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     565def : Pat<(fmul (fsub (fmul (vector_shuffle_1_1 DFRC:$A, undef), 
     566                            (vector_shuffle_1_0 DFRC:$C, undef)), 
     567            (fmul DFRC:$B, (v2f64 build_vector_neg1_1))), (v2f64 build_vector_1_neg1)), 
     568          (FXCXNSMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     569 
     570def : Pat<(fadd (fmul (vector_shuffle_1_1 DFRC:$A, undef), 
     571                            (vector_shuffle_1_0 DFRC:$C, undef)), DFRC:$B), 
     572          (FXCXMA DFRC:$A, DFRC:$B, DFRC:$C)>; 
     573 
     574def : Pat<(fneg (fsub (fmul (vector_shuffle_1_1 DFRC:$A, undef), 
     575                            (vector_shuffle_1_0 DFRC:$C, undef)), DFRC:$B)), 
     576          (FXCXNMS DFRC:$A, DFRC:$B, DFRC:$C)>; 
     577 
     578// Convert and Round Instructions 
     579def : Pat<(int_ppc_fp2_fpctiw DFRC:$A), 
     580          (FPCTIW DFRC:$A)>; 
     581 
     582// Move Instructions 
     583def : Pat<(int_ppc_fp2_fpneg DFRC:$A), 
     584          (FPNEG DFRC:$A)>; 
     585def : Pat<(int_ppc_fp2_fpabs DFRC:$A), 
     586          (FPABS DFRC:$A)>; 
     587def : Pat<(int_ppc_fp2_fpnabs DFRC:$A), 
     588          (FPNABS DFRC:$A)>; 
     589def : Pat<(int_ppc_fp2_fxmr DFRC:$A), 
     590          (FXMR DFRC:$A)>; 
     591 
     592// Load indexed instructions 
     593def : Pat<(int_ppc_fp2_lfpd xoaddr:$src), 
     594          (LFPDX xoaddr:$src)>; 
     595def : Pat<(int_ppc_fp2_lfps xoaddr:$src), 
     596          (LFPSX xoaddr:$src)>; 
     597def : Pat<(int_ppc_fp2_lfxd xoaddr:$src), 
     598          (LFXDX xoaddr:$src)>; 
     599def : Pat<(int_ppc_fp2_lfxs xoaddr:$src), 
     600          (LFXSX xoaddr:$src)>; 
     601 
     602// Store indexed instructions 
     603def : Pat<(int_ppc_fp2_stfpd DFRC:$T, xoaddr:$dst), 
     604          (STFPDX DFRC:$T, xoaddr:$dst)>; 
     605def : Pat<(int_ppc_fp2_stfps DFRC:$T, xoaddr:$dst), 
     606          (STFPSX DFRC:$T, xoaddr:$dst)>; 
     607def : Pat<(int_ppc_fp2_stfpiw DFRC:$T, xoaddr:$dst), 
     608          (STFPIWX DFRC:$T, xoaddr:$dst)>; 
     609def : Pat<(int_ppc_fp2_stfxd DFRC:$T, xoaddr:$dst), 
     610          (STFXDX DFRC:$T, xoaddr:$dst)>; 
     611def : Pat<(int_ppc_fp2_stfxs DFRC:$T, xoaddr:$dst), 
     612          (STFXSX DFRC:$T, xoaddr:$dst)>; 
  • lib/Target/PowerPC/PPCInstrFormats.td

    diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
    index d8e4b2b..bee5d21 100644
    a b  
    389389  let Inst{31}    = 0; 
    390390} 
    391391 
     392// Used for FP2 and QPX 
     393class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
     394               InstrItinClass itin, list<dag> pattern> 
     395         : I<opcode, OOL, IOL, asmstr, itin> { 
     396  bits<5> FRT; 
     397  bits<5> FRA; 
     398  bits<5> FRB; 
     399 
     400  let Pattern = pattern; 
     401   
     402  let Inst{6-10}  = FRT; 
     403  let Inst{11-15} = FRA; 
     404  let Inst{16-20} = FRB; 
     405  let Inst{21-30} = xo; 
     406  let Inst{31}    = 0; 
     407} 
     408 
     409class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
     410              InstrItinClass itin, list<dag> pattern>  
     411  : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 
     412  let FRA = 0; 
     413} 
     414 
     415class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 
     416               InstrItinClass itin, list<dag> pattern> 
     417         : I<opcode, OOL, IOL, asmstr, itin> { 
     418  bits<5> FRT; 
     419  bits<5> FRA; 
     420  bits<5> FRB; 
     421  bits<4> tttt; 
     422 
     423  let Pattern = pattern; 
     424   
     425  let Inst{6-10}  = FRT; 
     426  let Inst{11-15} = FRA; 
     427  let Inst{16-20} = FRB; 
     428  let Inst{21-24} = tttt; 
     429  let Inst{25-30} = xo; 
     430  let Inst{31}    = 0; 
     431} 
     432 
    392433class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
    393434               InstrItinClass itin, list<dag> pattern>  
    394435  : I<opcode, OOL, IOL, asmstr, itin> { 
     
    752793  let FRB = 0; 
    753794} 
    754795 
     796class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 
     797              InstrItinClass itin, list<dag> pattern> 
     798  : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 
     799  let FRA = 0; 
     800  let FRC = 0; 
     801} 
     802 
    755803// 1.7.13 M-Form 
    756804class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 
    757805              InstrItinClass itin, list<dag> pattern> 
     
    9571005  let Inst{22-31} = xo; 
    9581006} 
    9591007 
     1008// Z23-Form (used by QPX) 
     1009class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,  
     1010              InstrItinClass itin, list<dag> pattern> 
     1011         : I<opcode, OOL, IOL, asmstr, itin> { 
     1012  bits<5> FRT; 
     1013  bits<5> FRA; 
     1014  bits<5> FRB; 
     1015  bits<2> idx; 
     1016 
     1017  let Pattern = pattern; 
     1018 
     1019  bit RC = 0;    // set by isDOT 
     1020 
     1021  let Inst{6-10}  = FRT; 
     1022  let Inst{11-15} = FRA; 
     1023  let Inst{16-20} = FRB; 
     1024  let Inst{21-22} = idx; 
     1025  let Inst{23-30} = xo; 
     1026  let Inst{31}    = RC; 
     1027} 
     1028 
     1029class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 
     1030              InstrItinClass itin, list<dag> pattern> 
     1031  : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 
     1032  let FRB = 0; 
     1033} 
     1034 
     1035class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,  
     1036              InstrItinClass itin, list<dag> pattern> 
     1037         : I<opcode, OOL, IOL, asmstr, itin> { 
     1038  bits<5> FRT; 
     1039  bits<12> idx; 
     1040 
     1041  let Pattern = pattern; 
     1042 
     1043  bit RC = 0;    // set by isDOT 
     1044 
     1045  let Inst{6-10}  = FRT; 
     1046  let Inst{11-22} = idx; 
     1047  let Inst{23-30} = xo; 
     1048  let Inst{31}    = RC; 
     1049} 
     1050 
    9601051//===----------------------------------------------------------------------===// 
    9611052class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 
    9621053    : I<0, OOL, IOL, asmstr, NoItinerary> { 
  • lib/Target/PowerPC/PPCInstrInfo.cpp

    diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
    index c0b9e92..c2d4c15 100644
    a b  
    333333    Opc = PPC::MCRF; 
    334334  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 
    335335    Opc = PPC::VOR; 
     336  else if (PPC::DFRCRegClass.contains(DestReg, SrcReg)) 
     337    Opc = PPC::FPMR; 
     338  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg)) 
     339    Opc = PPC::QVFMR; 
    336340  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 
    337341    Opc = PPC::CROR; 
    338342  else 
     
    484488                     .addReg(SrcReg, getKillRegState(isKill)) 
    485489                     .addReg(PPC::R0) 
    486490                     .addReg(PPC::R0)); 
     491  } else if (RC == &PPC::DFRCRegClass) { 
     492    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFPDX)) 
     493                                       .addReg(SrcReg, 
     494                                               getKillRegState(isKill)), 
     495                                       FrameIdx)); 
     496  } else if (RC == &PPC::QFRCRegClass) { 
     497    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX)) 
     498                                       .addReg(SrcReg, 
     499                                               getKillRegState(isKill)), 
     500                                       FrameIdx)); 
    487501  } else { 
    488502    llvm_unreachable("Unknown regclass!"); 
    489503  } 
     
    619633                                       FrameIdx, 0, 0)); 
    620634    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0) 
    621635                     .addReg(PPC::R0)); 
     636  } else if (RC == &PPC::DFRCRegClass) { 
     637    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFPDX), DestReg), 
     638                                       FrameIdx)); 
     639  } else if (RC == &PPC::QFRCRegClass) { 
     640    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg), 
     641                                       FrameIdx)); 
    622642  } else { 
    623643    llvm_unreachable("Unknown regclass!"); 
    624644  } 
  • lib/Target/PowerPC/PPCInstrInfo.td

    diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
    index 748486c..30d9ac0 100644
    a b  
    5555 
    5656def SDT_PPCnop : SDTypeProfile<0, 0, []>; 
    5757 
     58def SDT_PPCqvfperm   : SDTypeProfile<1, 3, [ 
     59  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3> 
     60]>; 
     61def SDT_PPCqvgpci   : SDTypeProfile<1, 1, [ 
     62  SDTCisVec<0>, SDTCisInt<1> 
     63]>; 
     64def SDT_PPCqvaligni   : SDTypeProfile<1, 3, [ 
     65  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 
     66]>; 
     67def SDT_PPCqvesplati   : SDTypeProfile<1, 2, [ 
     68  SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 
     69]>; 
     70 
    5871//===----------------------------------------------------------------------===// 
    5972// PowerPC specific DAG Nodes. 
    6073// 
     
    93106 
    94107def PPCvperm    : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 
    95108 
     109def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>; 
     110def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>; 
     111def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>; 
     112def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>; 
     113 
    96114// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 
    97115// amounts.  These nodes are generated by the multi-precision shift code. 
    98116def PPCsrl        : SDNode<"PPCISD::SRL"       , SDTIntShiftOp>; 
     
    271289//===----------------------------------------------------------------------===// 
    272290// PowerPC Operand Definitions. 
    273291 
     292def u2imm   : Operand<i32> { 
     293  let PrintMethod = "printU2ImmOperand"; 
     294} 
    274295def s5imm   : Operand<i32> { 
    275296  let PrintMethod = "printS5ImmOperand"; 
    276297} 
     
    280301def u6imm   : Operand<i32> { 
    281302  let PrintMethod = "printU6ImmOperand"; 
    282303} 
     304def u12imm  : Operand<i32> { 
     305  let PrintMethod = "printU12ImmOperand"; 
     306} 
    283307def s16imm  : Operand<i32> { 
    284308  let PrintMethod = "printS16ImmOperand"; 
    285309} 
     
    441465} 
    442466 
    443467// Darwin ABI Calls. 
    444 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 
     468let isCall = 1, PPC970_Unit = 7, 
     469  Defs = [LR, 
     470          F0_ext,F1_ext,F2_ext,F3_ext,F4_ext,F5_ext,F6_ext,F7_ext,F8_ext,F9_ext, 
     471          F10_ext,F11_ext,F12_ext,F13_ext,F14_ext,F15_ext,F16_ext,F17_ext,F18_ext,F19_ext, 
     472          F20_ext,F21_ext,F22_ext,F23_ext,F24_ext,F25_ext,F26_ext,F27_ext,F28_ext,F29_ext, 
     473          F30_ext,F31_ext] in { 
    445474  // Convenient aliases for call instructions 
    446475  let Uses = [RM] in { 
    447476    def BL_Darwin  : IForm<18, 0, 1, 
     
    460489} 
    461490 
    462491// SVR4 ABI Calls. 
    463 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 
     492let isCall = 1, PPC970_Unit = 7, 
     493  Defs = [LR, 
     494          F0_ext,F1_ext,F2_ext,F3_ext,F4_ext,F5_ext,F6_ext,F7_ext,F8_ext,F9_ext, 
     495          F10_ext,F11_ext,F12_ext,F13_ext,F14_ext,F15_ext,F16_ext,F17_ext,F18_ext,F19_ext, 
     496          F20_ext,F21_ext,F22_ext,F23_ext,F24_ext,F25_ext,F26_ext,F27_ext,F28_ext,F29_ext, 
     497          F30_ext,F31_ext] in { 
    464498  // Convenient aliases for call instructions 
    465499  let Uses = [RM] in { 
    466500    def BL_SVR4  : IForm<18, 0, 1, 
     
    14801514def : Pat<(atomic_fence (imm), (imm)), (SYNC)>; 
    14811515 
    14821516include "PPCInstrAltivec.td" 
     1517include "PPCInstrFP2.td" 
    14831518include "PPCInstr64Bit.td" 
     1519include "PPCInstrQPX.td" 
  • (a) /dev/null vs. (b) b/lib/Target/PowerPC/PPCInstrQPX.td

    diff --git a/lib/Target/PowerPC/PPCInstrQPX.td b/lib/Target/PowerPC/PPCInstrQPX.td
    new file mode 100644
    index 0000000..e9d4948
    a b  
     1//===- PPCInstrQPX.td - The PowerPC QPX Extension --*- tablegen -*-===// 
     2//  
     3//                     The LLVM Compiler Infrastructure 
     4// 
     5// This file is distributed under the University of Illinois Open Source 
     6// License. See LICENSE.TXT for details. 
     7//  
     8//===----------------------------------------------------------------------===// 
     9// 
     10// This file describes the QPX extension to the PowerPC instruction set. 
     11// Reference: 
     12// Book Q: QPX Architecture Definition. IBM (as updated in) 2011. 
     13// 
     14//===----------------------------------------------------------------------===// 
     15 
     16//===----------------------------------------------------------------------===// 
     17// Helpers for defining instructions that directly correspond to intrinsics. 
     18 
     19// QPXA1_Int - A AForm_1 intrinsic definition. 
     20class QPXA1_Int<bits<6> opcode, bits<5> xo, string opc, Intrinsic IntID> 
     21  : AForm_1<opcode, xo, (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB, QFRC:$FRC), 
     22              !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), FPGeneral, 
     23                       [(set QFRC:$FRT, (IntID QFRC:$FRA, QFRC:$FRB, QFRC:$FRC))]>; 
     24// QPXA2_Int - A AForm_2 intrinsic definition. 
     25class QPXA2_Int<bits<6> opcode, bits<5> xo, string opc, Intrinsic IntID> 
     26  : AForm_2<opcode, xo, (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRC), 
     27              !strconcat(opc, " $FRT, $FRA, $FRC"), FPGeneral, 
     28                       [(set QFRC:$FRT, (IntID QFRC:$FRA, QFRC:$FRC))]>; 
     29// QPXA3_Int - A AForm_3 intrinsic definition. 
     30class QPXA3_Int<bits<6> opcode, bits<5> xo, string opc, Intrinsic IntID> 
     31  : AForm_3<opcode, xo, (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRC), 
     32              !strconcat(opc, " $FRT, $FRA, $FRC"), FPGeneral, 
     33                       [(set QFRC:$FRT, (IntID QFRC:$FRA, QFRC:$FRC))]>; 
     34// QPXA4_Int - A AForm_4 intrinsic definition. 
     35class QPXA4_Int<bits<6> opcode, bits<5> xo, string opc, Intrinsic IntID> 
     36  : AForm_4<opcode, xo, (outs QFRC:$FRT), (ins QFRC:$FRB), 
     37              !strconcat(opc, " $FRT, $FRB"), FPGeneral, 
     38                       [(set QFRC:$FRT, (IntID QFRC:$FRB))]>; 
     39// QPXX18_Int - A XForm_18 intrinsic definition. 
     40class QPXX18_Int<bits<6> opcode, bits<10> xo, string opc, Intrinsic IntID> 
     41  : XForm_18<opcode, xo, (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB), 
     42              !strconcat(opc, " $FRT, $FRA, $FRB"), FPCompare, 
     43                       [(set QFRC:$FRT, (IntID QFRC:$FRA, QFRC:$FRB))]>; 
     44// QPXX19_Int - A XForm_19 intrinsic definition. 
     45class QPXX19_Int<bits<6> opcode, bits<10> xo, string opc, Intrinsic IntID> 
     46  : XForm_19<opcode, xo, (outs QFRC:$FRT), (ins QFRC:$FRB), 
     47              !strconcat(opc, " $FRT, $FRB"), FPGeneral, 
     48                       [(set QFRC:$FRT, (IntID QFRC:$FRB))]>; 
     49 
     50//===----------------------------------------------------------------------===// 
     51// Pattern Frags. 
     52 
     53def extloadv4f32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 
     54  return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4f32; 
     55}]>; 
     56 
     57def truncstorev4f32 : PatFrag<(ops node:$val, node:$ptr), 
     58                            (truncstore node:$val, node:$ptr), [{ 
     59  return cast<StoreSDNode>(N)->getMemoryVT() == MVT::v4f32; 
     60}]>; 
     61 
     62def vector_shuffle_0_1_0_1 : PatFrag<(ops node:$lhs, node:$rhs), 
     63                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     64  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     65  return SV->getValueType(0).getVectorNumElements() == 4 && 
     66         SV->getMaskElt(0) == 0 && SV->getMaskElt(1) == 1 && 
     67         SV->getMaskElt(2) == 0 && SV->getMaskElt(3) == 1; 
     68}]>; 
     69 
     70def vector_shuffle_0_1 : PatFrag<(ops node:$lhs, node:$rhs), 
     71                              (vector_shuffle node:$lhs, node:$rhs), [{ 
     72  ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 
     73  return SV->getValueType(0).getVectorNumElements() == 2 && 
     74         SV->getMaskElt(0) == 0 && SV->getMaskElt(1) == 1; 
     75}]>; 
     76 
     77//===----------------------------------------------------------------------===// 
     78// Instruction Definitions. 
     79 
     80let Uses = [RM] in { 
     81  // Add Instructions 
     82  let isCommutable = 1 in { 
     83    def QVFADD : AForm_2<4, 21, 
     84                        (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB), 
     85                        "qvfadd $FRT, $FRA, $FRB", FPGeneral, 
     86                        [(set QFRC:$FRT, (fadd QFRC:$FRA, QFRC:$FRB))]>; 
     87    def QVFADDS : QPXA2_Int<0, 21, "qvfadds", int_ppc_qpx_qvfadds>; 
     88  } 
     89  def QVFSUB : AForm_2<4, 20, 
     90                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB), 
     91                      "qvfsub $FRT, $FRA, $FRB", FPGeneral, 
     92                      [(set QFRC:$FRT, (fsub QFRC:$FRA, QFRC:$FRB))]>; 
     93  def QVFSUBS : QPXA2_Int<0, 20, "qvfsubs", int_ppc_qpx_qvfsubs>; 
     94 
     95  // Estimate Instructions 
     96  def QVFRE : QPXA4_Int<4, 24, "qvfre", int_ppc_qpx_qvfre>; 
     97  def QVFRES : QPXA4_Int<0, 24, "qvfre", int_ppc_qpx_qvfres>; 
     98  def QVFRSQRTE : QPXA4_Int<4, 26, "qvfrsqrte", int_ppc_qpx_qvfrsqrte>; 
     99  def QVFRSQRTES : QPXA4_Int<0, 26, "qvfrsqrtes", int_ppc_qpx_qvfrsqrtes>; 
     100 
     101  // Multiply Instructions 
     102  let isCommutable = 1 in { 
     103    def QVFMUL : AForm_3<4, 25, 
     104                        (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB), 
     105                        "qvfmul $FRT, $FRA, $FRB", FPGeneral, 
     106                        [(set QFRC:$FRT, (fmul QFRC:$FRA, QFRC:$FRB))]>; 
     107    def QVFMULS : QPXA3_Int<0, 20, "qvfmuls", int_ppc_qpx_qvfmuls>; 
     108  } 
     109  def QVFXMUL : QPXA3_Int<4, 17, "qvfxmul", int_ppc_qpx_qvfxmul>; 
     110  def QVFXMULS : QPXA3_Int<0, 17, "qvfxmul", int_ppc_qpx_qvfxmuls>; 
     111 
     112  // Multiply-add instructions 
     113  def QVFMADD : AForm_1<4, 29, 
     114                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB, QFRC:$FRC), 
     115                      "qvfmadd $FRT, $FRA, $FRC, $FRB", FPGeneral, 
     116                      [(set QFRC:$FRT, (fadd (fmul QFRC:$FRA, QFRC:$FRC), 
     117                                             QFRC:$FRB))]>, 
     118                      Requires<[FPContractions]>; 
     119  def QVFMADDS : QPXA1_Int<0, 29, "qvfmadds", int_ppc_qpx_qvfmadds>; 
     120  def QVFNMADD : AForm_1<4, 31, 
     121                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB, QFRC:$FRC), 
     122                      "qvfnmadd $FRT, $FRA, $FRC, $FRB", FPGeneral, 
     123                      [(set QFRC:$FRT, (fneg (fadd (fmul QFRC:$FRA, QFRC:$FRC), 
     124                                             QFRC:$FRB)))]>, 
     125                      Requires<[FPContractions]>; 
     126  def QVFNMADDS : QPXA1_Int<0, 31, "qvfnmadds", int_ppc_qpx_qvfnmadds>; 
     127  def QVFMSUB : AForm_1<4, 28, 
     128                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB, QFRC:$FRC), 
     129                      "qvfmsub $FRT, $FRA, $FRC, $FRB", FPGeneral, 
     130                      [(set QFRC:$FRT, (fsub (fmul QFRC:$FRA, QFRC:$FRC), 
     131                                             QFRC:$FRB))]>, 
     132                      Requires<[FPContractions]>; 
     133  def QVFMSUBS : QPXA1_Int<0, 28, "qvfmsubs", int_ppc_qpx_qvfmsubs>; 
     134  def QVFNMSUB : AForm_1<4, 30, 
     135                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB, QFRC:$FRC), 
     136                      "qvfnmsub $FRT, $FRA, $FRC, $FRB", FPGeneral, 
     137                      [(set QFRC:$FRT, (fneg (fsub (fmul QFRC:$FRA, QFRC:$FRC), 
     138                                             QFRC:$FRB)))]>, 
     139                      Requires<[FPContractions]>; 
     140  def QVFNMSUBS : QPXA1_Int<0, 30, "qvfnmsubs", int_ppc_qpx_qvfnmsubs>; 
     141  def QVFXMADD : QPXA1_Int<4, 9, "qvfxmadd", int_ppc_qpx_qvfxmadd>; 
     142  def QVFXMADDS : QPXA1_Int<0, 9, "qvfxmadds", int_ppc_qpx_qvfxmadds>; 
     143  def QVFXXNPMADD : QPXA1_Int<4, 11, "qvfxxnpmadd", int_ppc_qpx_qvfxxnpmadd>; 
     144  def QVFXXNPMADDS : QPXA1_Int<0, 11, "qvfxxnpmadds", int_ppc_qpx_qvfxxnpmadds>; 
     145  def QVFXXCPNMADD : QPXA1_Int<4, 3, "qvfxxcpnmadd", int_ppc_qpx_qvfxxcpnmadd>; 
     146  def QVFXXCPNMADDS : QPXA1_Int<0, 3, "qvfxxcpnmadds", int_ppc_qpx_qvfxxcpnmadds>; 
     147  def QVFXXMADD : QPXA1_Int<4, 1, "qvfxxmadd", int_ppc_qpx_qvfxxmadd>; 
     148  def QVFXXMADDS : QPXA1_Int<4, 1, "qvfxxmadds", int_ppc_qpx_qvfxxmadds>; 
     149 
     150  // Select Instruction 
     151  def QVFSEL : QPXA1_Int<4, 23, "qvfsel", int_ppc_qpx_qvfsel>; 
     152 
     153  // Convert and Round Instructions 
     154  def QVFCTID : QPXX19_Int<4, 814, "qvfctid", int_ppc_qpx_qvfctid>; 
     155  def QVFCTIDU : QPXX19_Int<4, 942, "qvfctidu", int_ppc_qpx_qvfctidu>; 
     156  def QVFCTIDZ : QPXX19_Int<4, 815, "qvfctidz", int_ppc_qpx_qvfctidz>; 
     157  def QVFCTIDUZ : QPXX19_Int<4, 143, "qvfctiduz", int_ppc_qpx_qvfctiduz>; 
     158  def QVFCTIW : QPXX19_Int<4, 14, "qvfctiw", int_ppc_qpx_qvfctiw>; 
     159  def QVFCTIWU : QPXX19_Int<4, 142, "qvfctiwu", int_ppc_qpx_qvfctiwu>; 
     160  def QVFCTIWZ : QPXX19_Int<4, 15, "qvfctiwz", int_ppc_qpx_qvfctiwz>; 
     161  def QVFCTIWUZ : QPXX19_Int<4, 943, "qvfctiwuz", int_ppc_qpx_qvfctiwuz>; 
     162  def QVFCFID : QPXX19_Int<4, 846, "qvfcfid", int_ppc_qpx_qvfcfid>; 
     163  def QVFCFIDU : QPXX19_Int<4, 974, "qvfcfidu", int_ppc_qpx_qvfcfidu>; 
     164  def QVFCFIDS : QPXX19_Int<0, 846, "qvfcfids", int_ppc_qpx_qvfcfids>; 
     165  def QVFCFIDUS : QPXX19_Int<0, 974, "qvfcfidus", int_ppc_qpx_qvfcfidus>; 
     166 
     167  def QVFRSP : QPXX19_Int<4, 12, "qvfrsp", int_ppc_qpx_qvfrsp>; 
     168  def QVFRIZ : QPXX19_Int<4, 424, "qvfriz", int_ppc_qpx_qvfriz>; 
     169  def QVFRIN : QPXX19_Int<4, 392, "qvfrin", int_ppc_qpx_qvfrin>; 
     170  def QVFRIP : QPXX19_Int<4, 456, "qvfrip", int_ppc_qpx_qvfrip>; 
     171  def QVFRIM : QPXX19_Int<4, 488, "qvfrim", int_ppc_qpx_qvfrim>; 
     172 
     173  // Move Instructions 
     174  def QVFMR : XForm_19<4, 74, 
     175                      (outs QFRC:$FRT), (ins QFRC:$FRB), 
     176                      "qvfmr $FRT, $FRB", FPGeneral, 
     177                      [/* (set QFRC:$FRT, QFRC:$FRB) */]>; 
     178  def QVFNEG : XForm_19<4, 40, 
     179                      (outs QFRC:$FRT), (ins QFRC:$FRB), 
     180                      "qvfneg $FRT, $FRB", FPGeneral, 
     181                      [(set QFRC:$FRT, (fneg QFRC:$FRB))]>; 
     182  def QVFABS : XForm_19<4, 264, 
     183                      (outs QFRC:$FRT), (ins QFRC:$FRB), 
     184                      "qvfabs $FRT, $FRB", FPGeneral, 
     185                      [(set QFRC:$FRT, (fabs QFRC:$FRB))]>; 
     186  def QVFNABS : XForm_19<4, 136, 
     187                      (outs QFRC:$FRT), (ins QFRC:$FRB), 
     188                      "qvfnabs $FRT, $FRB", FPGeneral, 
     189                      [(set QFRC:$FRT, (fneg (fabs QFRC:$FRB)))]>; 
     190  def QVFCPSGN : XForm_18<4, 74, 
     191                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB), 
     192                      "qvfcpsgn $FRT, $FRA, $FRB", FPGeneral, []>; 
     193 
     194  def QVALIGNI : Z23Form_1<4, 5, 
     195                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB, u2imm:$idx), 
     196                      "qvaligni $FRT, $FRA, $FRB, $idx", FPGeneral, 
     197                      [(set QFRC:$FRT, 
     198                          (PPCqvaligni QFRC:$FRA, QFRC:$FRB, (i32 imm:$idx)))]>; 
     199  def QVESPLATI : Z23Form_2<4, 37, 
     200                      (outs QFRC:$FRT), (ins QFRC:$FRA, u2imm:$idx), 
     201                      "qvesplati $FRT, $FRA, $idx", FPGeneral, 
     202                      [(set QFRC:$FRT, 
     203                          (PPCqvesplati QFRC:$FRA, (i32 imm:$idx)))]>; 
     204  def QVFPERM : AForm_1<4, 6, 
     205                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB, QFRC:$FRC), 
     206                      "qvfperm $FRT, $FRA, $FRB, $FRC", FPGeneral, 
     207                      [(set QFRC:$FRT, 
     208                          (PPCqvfperm QFRC:$FRA, QFRC:$FRB, QFRC:$FRC))]>; 
     209  def QVGPCI : Z23Form_3<4, 133, 
     210                      (outs QFRC:$FRT), (ins u12imm:$idx), 
     211                      "qvgpci $FRT, $idx", FPGeneral, 
     212                      [(set QFRC:$FRT, (PPCqvgpci (i32 imm:$idx)))]>; 
     213 
     214  // Compare Instruction 
     215  def QVFTSTNAN : QPXX18_Int<4, 64, "qvftstnan", int_ppc_qpx_qvftstnan>; 
     216  def QVFCMPLT : QPXX18_Int<4, 96, "qvfcmplt", int_ppc_qpx_qvfcmplt>; 
     217  def QVFCMPGT : QPXX18_Int<4, 32, "qvfcmpgt", int_ppc_qpx_qvfcmpgt>; 
     218  def QVFCMPEQ : QPXX18_Int<4, 0, "qvfcmpeq", int_ppc_qpx_qvfcmpeq>; 
     219 
     220  def QVFLOGICAL : XForm_20<4, 4, 
     221                      (outs QFRC:$FRT), (ins QFRC:$FRA, QFRC:$FRB, u12imm:$tttt), 
     222                      "qvflogical $FRT, $FRA, $FRB, $tttt", FPCompare, []>; 
     223 
     224  // Load indexed instructions 
     225  let canFoldAsLoad = 1 in { 
     226    def QVLFDX : XForm_1<31, 583, 
     227                        (outs QFRC:$FRT), (ins memrr:$src), 
     228                        "qvlfdx $FRT, $src", LdStLoad, 
     229                        [(set QFRC:$FRT, (load xoaddr:$src))]>; 
     230    let RC = 1 in 
     231    def QVLFDXA : XForm_1<31, 583, 
     232                        (outs QFRC:$FRT), (ins memrr:$src), 
     233                        "qvlfdxa $FRT, $src", LdStLoad, []>; 
     234 
     235    def QVLFDUX : XForm_1<31, 494, 
     236                        (outs QFRC:$FRT), (ins memrr:$src), 
     237                        "qvlfdux $FRT, $src", LdStLoad, []>; 
     238    let RC = 1 in 
     239    def QVLFDUXA : XForm_1<31, 494, 
     240                        (outs QFRC:$FRT), (ins memrr:$src), 
     241                        "qvlfduxa $FRT, $src", LdStLoad, []>; 
     242 
     243    def QVLFSX : XForm_1<31, 519, 
     244                        (outs QFRC:$FRT), (ins memrr:$src), 
     245                        "qvlfsx $FRT, $src", LdStLoad, 
     246                        [(set QFRC:$FRT, (extloadv4f32 xoaddr:$src))]>; 
     247    let RC = 1 in 
     248    def QVLFSXA : XForm_1<31, 519, 
     249                        (outs QFRC:$FRT), (ins memrr:$src), 
     250                        "qvlfsxa $FRT, $src", LdStLoad, []>; 
     251 
     252 
     253    def QVLFSUX : XForm_1<31, 615, 
     254                        (outs QFRC:$FRT), (ins memrr:$src), 
     255                        "qvlfsux $FRT, $src", LdStLoad, []>; 
     256    let RC = 1 in 
     257    def QVLFSUXA : XForm_1<31, 615, 
     258                        (outs QFRC:$FRT), (ins memrr:$src), 
     259                        "qvlfsuxa $FRT, $src", LdStLoad, []>; 
     260 
     261    def QVLFCDX : XForm_1<31, 71, 
     262                        (outs QFRC:$FRT), (ins memrr:$src), 
     263                        "qvlfcdx $FRT, $src", LdStLoad, 
     264                        [(set QFRC:$FRT, (vector_shuffle_0_1_0_1 (load xoaddr:$src), undef))]>; 
     265    let RC = 1 in 
     266    def QVLFCDXA : XForm_1<31, 71, 
     267                        (outs QFRC:$FRT), (ins memrr:$src), 
     268                        "qvlfcdxa $FRT, $src", LdStLoad, []>; 
     269 
     270    def QVLFCDUX : XForm_1<31, 103, 
     271                        (outs QFRC:$FRT), (ins memrr:$src), 
     272                        "qvlfcdux $FRT, $src", LdStLoad, []>; 
     273    let RC = 1 in 
     274    def QVLFCDUXA : XForm_1<31, 103, 
     275                        (outs QFRC:$FRT), (ins memrr:$src), 
     276                        "qvlfcduxa $FRT, $src", LdStLoad, []>; 
     277 
     278    def QVLFCSX : XForm_1<31, 7, 
     279                        (outs QFRC:$FRT), (ins memrr:$src), 
     280                        "qvlfcsx $FRT, $src", LdStLoad, 
     281                        [(set QFRC:$FRT, (vector_shuffle_0_1_0_1 (extloadv2f32 xoaddr:$src), undef))]>; 
     282    let RC = 1 in 
     283    def QVLFCSXA : XForm_1<31, 7, 
     284                        (outs QFRC:$FRT), (ins memrr:$src), 
     285                        "qvlfcsxa $FRT, $src", LdStLoad, []>; 
     286 
     287    def QVLFCSUX : XForm_1<31, 39, 
     288                        (outs QFRC:$FRT), (ins memrr:$src), 
     289                        "qvlfcsux $FRT, $src", LdStLoad, []>; 
     290    let RC = 1 in 
     291    def QVLFCSUXA : XForm_1<31, 39, 
     292                        (outs QFRC:$FRT), (ins memrr:$src), 
     293                        "qvlfcsuxa $FRT, $src", LdStLoad, []>; 
     294 
     295    def QVLFIWAX : XForm_1<31, 871, 
     296                        (outs QFRC:$FRT), (ins memrr:$src), 
     297                        "qvlfiwax $FRT, $src", LdStLoad, []>; 
     298    let RC = 1 in 
     299    def QVLFIWAXA : XForm_1<31, 871, 
     300                        (outs QFRC:$FRT), (ins memrr:$src), 
     301                        "qvlfiwaxa $FRT, $src", LdStLoad, []>; 
     302 
     303    def QVLFIWZX : XForm_1<31, 839, 
     304                        (outs QFRC:$FRT), (ins memrr:$src), 
     305                        "qvlfiwzx $FRT, $src", LdStLoad, []>; 
     306    let RC = 1 in 
     307    def QVLFIWZXA : XForm_1<31, 839, 
     308                        (outs QFRC:$FRT), (ins memrr:$src), 
     309                        "qvlfiwzxa $FRT, $src", LdStLoad, []>; 
     310 
     311    def QVLPCLDX : XForm_1<31, 582, 
     312                        (outs QFRC:$FRT), (ins memrr:$src), 
     313                        "qvlpcldx $FRT, $src", LdStLoad, []>; 
     314    def QVLPCLSX : XForm_1<31, 518, 
     315                        (outs QFRC:$FRT), (ins memrr:$src), 
     316                        "qvlpclsx $FRT, $src", LdStLoad, []>; 
     317    def QVLPCRDX : XForm_1<31, 70, 
     318                        (outs QFRC:$FRT), (ins memrr:$src), 
     319                        "qvlpcrdx $FRT, $src", LdStLoad, []>; 
     320    def QVLPCRSX : XForm_1<31, 6, 
     321                        (outs QFRC:$FRT), (ins memrr:$src), 
     322                        "qvlpcrsx $FRT, $src", LdStLoad, []>; 
     323  } 
     324 
     325  // Store indexed instructions 
     326  def QVSTFDX : XForm_8<31, 711, 
     327                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     328                      "qvstfdx $FRT, $dst", LdStStore, 
     329                      [(store QFRC:$FRT, xoaddr:$dst)]>; 
     330  let RC = 1 in 
     331  def QVSTFDXA : XForm_8<31, 711, 
     332                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     333                      "qvstfdxa $FRT, $dst", LdStStore, []>; 
     334 
     335  def QVSTFDUX : XForm_8<31, 743, 
     336                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     337                      "qvstsdux $FRT, $dst", LdStStore, []>; 
     338  let RC = 1 in 
     339  def QVSTFDUXA : XForm_8<31, 743, 
     340                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     341                      "qvstsduxa $FRT, $dst", LdStStore, []>; 
     342 
     343  def QVSTFDXI : XForm_8<31, 709, 
     344                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     345                      "qvstsdxi $FRT, $dst", LdStStore, []>; 
     346  let RC = 1 in 
     347  def QVSTFDXIA : XForm_8<31, 709, 
     348                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     349                      "qvstsdxia $FRT, $dst", LdStStore, []>; 
     350 
     351  def QVSTFDUXI : XForm_8<31, 741, 
     352                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     353                      "qvstsduxi $FRT, $dst", LdStStore, []>; 
     354  let RC = 1 in 
     355  def QVSTFDUXIA : XForm_8<31, 741, 
     356                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     357                      "qvstsduxia $FRT, $dst", LdStStore, []>; 
     358 
     359  def QVSTFSX : XForm_8<31, 647, 
     360                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     361                      "qvstfsx $FRT, $dst", LdStStore, 
     362                      [(truncstorev4f32 QFRC:$FRT, xoaddr:$dst)]>; 
     363  let RC = 1 in 
     364  def QVSTFSXA : XForm_8<31, 647, 
     365                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     366                      "qvstfsxa $FRT, $dst", LdStStore, []>; 
     367 
     368  def QVSTFSUX : XForm_8<31, 679, 
     369                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     370                      "qvstfsux $FRT, $dst", LdStStore, []>; 
     371  let RC = 1 in 
     372  def QVSTFSUXA : XForm_8<31, 679, 
     373                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     374                      "qvstfsuxa $FRT, $dst", LdStStore, []>; 
     375 
     376  def QVSTFSXI : XForm_8<31, 645, 
     377                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     378                      "qvstfsxi $FRT, $dst", LdStStore, []>; 
     379  let RC = 1 in 
     380  def QVSTFSXIA : XForm_8<31, 645, 
     381                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     382                      "qvstfsxia $FRT, $dst", LdStStore, []>; 
     383 
     384  def QVSTFSUXI : XForm_8<31, 677, 
     385                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     386                      "qvstfsuxi $FRT, $dst", LdStStore, []>; 
     387  let RC = 1 in 
     388  def QVSTFSUXIA : XForm_8<31, 677, 
     389                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     390                      "qvstfsuxia $FRT, $dst", LdStStore, []>; 
     391 
     392  def QVSTFCDX : XForm_8<31, 199, 
     393                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     394                      "qvstfcdx $FRT, $dst", LdStStore, 
     395                      [(store (vector_shuffle_0_1 QFRC:$FRT, undef), xoaddr:$dst)]>; 
     396  let RC = 1 in 
     397  def QVSTFCDXA : XForm_8<31, 199, 
     398                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     399                      "qvstfcdxa $FRT, $dst", LdStStore, []>; 
     400 
     401  def QVSTFCSX : XForm_8<31, 135, 
     402                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     403                      "qvstfcsx $FRT, $dst", LdStStore, 
     404                      [(truncstorev2f32 (vector_shuffle_0_1 QFRC:$FRT, undef), xoaddr:$dst)]>; 
     405  let RC = 1 in 
     406  def QVSTFCSXA : XForm_8<31, 135, 
     407                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     408                      "qvstfcsxa $FRT, $dst", LdStStore, []>; 
     409 
     410  def QVSTFCDUX : XForm_8<31, 231, 
     411                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     412                      "qvstfcdux $FRT, $dst", LdStStore, []>; 
     413  let RC = 1 in 
     414  def QVSTFCDUXA : XForm_8<31, 231, 
     415                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     416                      "qvstfcduxa $FRT, $dst", LdStStore, []>; 
     417 
     418  def QVSTFCSUX : XForm_8<31, 167, 
     419                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     420                      "qvstfcsux $FRT, $dst", LdStStore, []>; 
     421  let RC = 1 in 
     422  def QVSTFCSUXA : XForm_8<31, 167, 
     423                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     424                      "qvstfcsuxa $FRT, $dst", LdStStore, []>; 
     425 
     426  def QVSTFCDXI : XForm_8<31, 197, 
     427                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     428                      "qvstfcdxi $FRT, $dst", LdStStore, []>; 
     429  let RC = 1 in 
     430  def QVSTFCDXIA : XForm_8<31, 197, 
     431                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     432                      "qvstfcdxia $FRT, $dst", LdStStore, []>; 
     433 
     434  def QVSTFCSXI : XForm_8<31, 133, 
     435                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     436                      "qvstfcsxi $FRT, $dst", LdStStore, []>; 
     437  let RC = 1 in 
     438  def QVSTFCSXIA : XForm_8<31, 133, 
     439                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     440                      "qvstfcsxia $FRT, $dst", LdStStore, []>; 
     441 
     442  def QVSTFCDUXI : XForm_8<31, 229, 
     443                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     444                      "qvstfcduxi $FRT, $dst", LdStStore, []>; 
     445  let RC = 1 in 
     446  def QVSTFCDUXIA : XForm_8<31, 229, 
     447                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     448                      "qvstfcduxia $FRT, $dst", LdStStore, []>; 
     449 
     450  def QVSTFCSUXI : XForm_8<31, 165, 
     451                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     452                      "qvstfcsuxi $FRT, $dst", LdStStore, []>; 
     453  let RC = 1 in 
     454  def QVSTFCSUXIA : XForm_8<31, 165, 
     455                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     456                      "qvstfcsuxia $FRT, $dst", LdStStore, []>; 
     457 
     458  def QVSTFIWX : XForm_8<31, 977, 
     459                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     460                      "qvstfiwx $FRT, $dst", LdStStore, []>; 
     461  let RC = 1 in 
     462  def QVSTFIWXA : XForm_8<31, 977, 
     463                      (outs), (ins QFRC:$FRT, memrr:$dst), 
     464                      "qvstfiwxa $FRT, $dst", LdStStore, []>; 
     465 
     466} 
     467 
     468//===----------------------------------------------------------------------===// 
     469// Additional QPX Patterns 
     470// 
     471 
     472def : Pat<(v4f64 (scalar_to_vector F8RC:$A)), 
     473          (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), F8RC:$A, sub_64)>; 
     474 
     475def : Pat<(f64 (vector_extract QFRC:$S, 0)), 
     476          (EXTRACT_SUBREG QFRC:$S, sub_64)>; 
     477 
     478def : Pat<(f64 (vector_extract QFRC:$S, 1)), 
     479          (EXTRACT_SUBREG (QVESPLATI QFRC:$S, 1), sub_64)>; 
     480def : Pat<(f64 (vector_extract QFRC:$S, 2)), 
     481          (EXTRACT_SUBREG (QVESPLATI QFRC:$S, 2), sub_64)>; 
     482def : Pat<(f64 (vector_extract QFRC:$S, 3)), 
     483          (EXTRACT_SUBREG (QVESPLATI QFRC:$S, 3), sub_64)>; 
     484 
     485def : Pat<(int_ppc_qpx_qvfperm QFRC:$A, QFRC:$B, QFRC:$C), 
     486          (QVFPERM QFRC:$A, QFRC:$B, QFRC:$C)>; 
     487 
     488def : Pat<(int_ppc_qpx_qvfcpsgn QFRC:$A, QFRC:$B), 
     489          (QVFCPSGN QFRC:$A, QFRC:$B)>; 
     490 
     491def : Pat<(int_ppc_qpx_qvfneg QFRC:$A), (QVFNEG QFRC:$A)>; 
     492def : Pat<(int_ppc_qpx_qvfabs QFRC:$A), (QVFABS QFRC:$A)>; 
     493def : Pat<(int_ppc_qpx_qvfnabs QFRC:$A), (QVFNABS QFRC:$A)>; 
     494 
     495def : Pat<(int_ppc_qpx_qvfadd QFRC:$A, QFRC:$B), 
     496          (QVFADD QFRC:$A, QFRC:$B)>; 
     497def : Pat<(int_ppc_qpx_qvfsub QFRC:$A, QFRC:$B), 
     498          (QVFSUB QFRC:$A, QFRC:$B)>; 
     499def : Pat<(int_ppc_qpx_qvfmul QFRC:$A, QFRC:$B), 
     500          (QVFMUL QFRC:$A, QFRC:$B)>; 
     501 
     502def : Pat<(int_ppc_qpx_qvfmadd QFRC:$A, QFRC:$B, QFRC:$C), 
     503          (QVFMADD QFRC:$A, QFRC:$B, QFRC:$C)>; 
     504def : Pat<(int_ppc_qpx_qvfnmadd QFRC:$A, QFRC:$B, QFRC:$C), 
     505          (QVFNMADD QFRC:$A, QFRC:$B, QFRC:$C)>; 
     506def : Pat<(int_ppc_qpx_qvfmsub QFRC:$A, QFRC:$B, QFRC:$C), 
     507          (QVFMSUB QFRC:$A, QFRC:$B, QFRC:$C)>; 
     508def : Pat<(int_ppc_qpx_qvfnmsub QFRC:$A, QFRC:$B, QFRC:$C), 
     509          (QVFNMSUB QFRC:$A, QFRC:$B, QFRC:$C)>; 
     510 
     511def : Pat<(int_ppc_qpx_qvlfd xoaddr:$src), 
     512          (QVLFDX xoaddr:$src)>; 
     513def : Pat<(int_ppc_qpx_qvlfda xoaddr:$src), 
     514          (QVLFDXA xoaddr:$src)>; 
     515def : Pat<(int_ppc_qpx_qvlfs xoaddr:$src), 
     516          (QVLFSX xoaddr:$src)>; 
     517def : Pat<(int_ppc_qpx_qvlfsa xoaddr:$src), 
     518          (QVLFSXA xoaddr:$src)>; 
     519def : Pat<(int_ppc_qpx_qvlfcda xoaddr:$src), 
     520          (QVLFCDXA xoaddr:$src)>; 
     521def : Pat<(int_ppc_qpx_qvlfcd xoaddr:$src), 
     522          (QVLFCDX xoaddr:$src)>; 
     523def : Pat<(int_ppc_qpx_qvlfcsa xoaddr:$src), 
     524          (QVLFCSXA xoaddr:$src)>; 
     525def : Pat<(int_ppc_qpx_qvlfcs xoaddr:$src), 
     526          (QVLFCSX xoaddr:$src)>; 
     527def : Pat<(int_ppc_qpx_qvlfda xoaddr:$src), 
     528          (QVLFDXA xoaddr:$src)>; 
     529def : Pat<(int_ppc_qpx_qvlfiwaa xoaddr:$src), 
     530          (QVLFIWAXA xoaddr:$src)>; 
     531def : Pat<(int_ppc_qpx_qvlfiwa xoaddr:$src), 
     532          (QVLFIWAX xoaddr:$src)>; 
     533def : Pat<(int_ppc_qpx_qvlfiwza xoaddr:$src), 
     534          (QVLFIWZXA xoaddr:$src)>; 
     535def : Pat<(int_ppc_qpx_qvlfiwz xoaddr:$src), 
     536          (QVLFIWZX xoaddr:$src)>; 
     537def : Pat<(int_ppc_qpx_qvlfsa xoaddr:$src), 
     538          (QVLFSXA xoaddr:$src)>; 
     539def : Pat<(int_ppc_qpx_qvlpcld xoaddr:$src), 
     540          (QVLPCLDX xoaddr:$src)>; 
     541def : Pat<(int_ppc_qpx_qvlpcls xoaddr:$src), 
     542          (QVLPCLSX xoaddr:$src)>; 
     543def : Pat<(int_ppc_qpx_qvlpcrd xoaddr:$src), 
     544          (QVLPCRDX xoaddr:$src)>; 
     545def : Pat<(int_ppc_qpx_qvlpcrs xoaddr:$src), 
     546          (QVLPCRSX xoaddr:$src)>; 
     547 
     548def : Pat<(int_ppc_qpx_qvstfd QFRC:$T, xoaddr:$dst), 
     549          (QVSTFDX QFRC:$T, xoaddr:$dst)>; 
     550def : Pat<(int_ppc_qpx_qvstfs QFRC:$T, xoaddr:$dst), 
     551          (QVSTFSX QFRC:$T, xoaddr:$dst)>; 
     552def : Pat<(int_ppc_qpx_qvstfcda QFRC:$T, xoaddr:$dst), 
     553          (QVSTFCDXA QFRC:$T, xoaddr:$dst)>; 
     554def : Pat<(int_ppc_qpx_qvstfcd QFRC:$T, xoaddr:$dst), 
     555          (QVSTFCDX QFRC:$T, xoaddr:$dst)>; 
     556def : Pat<(int_ppc_qpx_qvstfcsa QFRC:$T, xoaddr:$dst), 
     557          (QVSTFCSXA QFRC:$T, xoaddr:$dst)>; 
     558def : Pat<(int_ppc_qpx_qvstfcs QFRC:$T, xoaddr:$dst), 
     559          (QVSTFCSX QFRC:$T, xoaddr:$dst)>; 
     560def : Pat<(int_ppc_qpx_qvstfda QFRC:$T, xoaddr:$dst), 
     561          (QVSTFDXA QFRC:$T, xoaddr:$dst)>; 
     562def : Pat<(int_ppc_qpx_qvstfiwa QFRC:$T, xoaddr:$dst), 
     563          (QVSTFIWXA QFRC:$T, xoaddr:$dst)>; 
     564def : Pat<(int_ppc_qpx_qvstfiw QFRC:$T, xoaddr:$dst), 
     565          (QVSTFIWX QFRC:$T, xoaddr:$dst)>; 
     566def : Pat<(int_ppc_qpx_qvstfsa QFRC:$T, xoaddr:$dst), 
     567          (QVSTFSXA QFRC:$T, xoaddr:$dst)>; 
     568 
     569def : Pat<(int_ppc_qpx_qvflogical  QFRC:$A, QFRC:$B, (i32 imm:$idx)), 
     570          (QVFLOGICAL QFRC:$A, QFRC:$B, imm:$idx)>; 
     571def : Pat<(int_ppc_qpx_qvgpci (i32 imm:$idx)), 
     572          (QVGPCI imm:$idx)>; 
     573 
  • lib/Target/PowerPC/PPCRegisterInfo.cpp

    diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
    index ecb8754..d21a659 100644
    a b  
    105105  return &PPC::GPRCRegClass; 
    106106} 
    107107 
     108const TargetRegisterClass * 
     109PPCRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 
     110                                          const TargetRegisterClass *B, 
     111                                          unsigned SubIdx) const { 
     112  switch (SubIdx) { 
     113  default: return 0; 
     114  case PPC::sub_64: 
     115    if (B == &PPC::F8RCRegClass) 
     116      return A; 
     117    break; 
     118  } 
     119  return 0; 
     120} 
     121 
    108122const uint16_t* 
    109123PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 
    110124  if (Subtarget.isDarwinABI()) 
     
    192206  } 
    193207  case PPC::F8RCRegClassID: 
    194208  case PPC::F4RCRegClassID: 
     209  case PPC::DFRCRegClassID: 
     210  case PPC::QFRCRegClassID: 
    195211  case PPC::VRRCRegClassID: 
    196212    return 32 - DefaultSafety; 
    197213  case PPC::CRRCRegClassID: 
     
    539555    isIXAddr = true; 
    540556    break; 
    541557  } 
     558 
     559  // If this is a FP2 or QPX instruction, then there is no imm form. 
     560  bool noImmForm = false; 
     561  switch (OpC) { 
     562  case PPC::LFPDX: 
     563  case PPC::LFPSX: 
     564  case PPC::LFSDX: 
     565  case PPC::LFSSX: 
     566  case PPC::LFXDX: 
     567  case PPC::LFXSX: 
     568  case PPC::STFPDX: 
     569  case PPC::STFPSX: 
     570  case PPC::STFPIWX: 
     571  case PPC::STFSDX: 
     572  case PPC::STFSSX: 
     573  case PPC::STFXDX: 
     574  case PPC::STFXSX: 
     575  case PPC::QVLFDX:  
     576  case PPC::QVLFSX:  
     577  case PPC::QVLFCDX:  
     578  case PPC::QVLFCSX:  
     579  case PPC::QVLFIWAX:  
     580  case PPC::QVLFIWZX:  
     581  case PPC::QVLPCLDX:  
     582  case PPC::QVLPCLSX:  
     583  case PPC::QVLPCRDX:  
     584  case PPC::QVLPCRSX:  
     585  case PPC::QVSTFDX:  
     586  case PPC::QVSTFSX:  
     587  case PPC::QVSTFCDX:  
     588  case PPC::QVSTFCSX:  
     589  case PPC::QVSTFIWX:  
     590    noImmForm = true; 
     591    break; 
     592  } 
    542593   
    543594  // Now add the frame object offset to the offset from r1. 
    544595  int Offset = MFI->getObjectOffset(FrameIndex); 
     
    562613  // only "std" to a stack slot that is at least 4-byte aligned, but it can 
    563614  // happen in invalid code. 
    564615  if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 
    565       (isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 
     616      (!noImmForm && 
     617       isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) { 
    566618    if (isIXAddr) 
    567619      Offset >>= 2;    // The actual encoded value has the low two bits zero. 
    568620    MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 
     
    593645  //   addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 
    594646  unsigned OperandBase; 
    595647 
    596   if (OpC != TargetOpcode::INLINEASM) { 
     648  if (noImmForm) 
     649    OperandBase = 1; 
     650  else if (OpC != TargetOpcode::INLINEASM) { 
    597651    assert(ImmToIdxMap.count(OpC) && 
    598652           "No indexed form of load or store available!"); 
    599653    unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 
  • lib/Target/PowerPC/PPCRegisterInfo.h

    diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
    index 78e17c6..be0d1fa 100644
    a b  
    3232  const TargetInstrInfo &TII; 
    3333public: 
    3434  PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii); 
     35 
     36  /// getMatchingSuperRegClass - Return a subclass of the specified register 
     37  /// class A so that each register in it has a sub-register of the 
     38  /// specified sub-register index which is in the specified register class B. 
     39  virtual const TargetRegisterClass * 
     40  getMatchingSuperRegClass(const TargetRegisterClass *A, 
     41                           const TargetRegisterClass *B, unsigned Idx) const; 
    3542   
    3643  /// getPointerRegClass - Return the register class to use to hold pointers. 
    3744  /// This is used for addressing modes. 
  • lib/Target/PowerPC/PPCRegisterInfo.td

    diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
    index 066a8fb..61e252d 100644
    a b  
    1616def sub_eq : SubRegIndex; 
    1717def sub_un : SubRegIndex; 
    1818def sub_32 : SubRegIndex; 
     19def sub_64 : SubRegIndex; 
     20def sub_fext : SubRegIndex; 
    1921} 
    2022 
    2123 
     
    4749  field bits<5> Num = num; 
    4850} 
    4951 
     52// The extended part of the FP2 or QPX registers (these are call-clobbered) 
     53class FPR_ext<string n> : PPCReg<n>; 
     54 
     55// DFPR - One of the 32 128-bit floating-point vector registers (used for FP2) 
     56class DFPR<FPR SubReg, FPR_ext SubReg_ext, string n> : PPCReg<n> { 
     57  field bits<5> Num = SubReg.Num; 
     58  let SubRegs = [SubReg, SubReg_ext]; 
     59  let SubRegIndices = [sub_64, sub_fext]; 
     60} 
     61 
     62// QFPR - One of the 32 256-bit floating-point vector registers (used for QPX) 
     63class QFPR<FPR SubReg, FPR_ext SubReg_ext, string n> : PPCReg<n> { 
     64  field bits<5> Num = SubReg.Num; 
     65  let SubRegs = [SubReg, SubReg_ext]; 
     66  let SubRegIndices = [sub_64, sub_fext]; 
     67} 
     68 
    5069// VR - One of the 32 128-bit vector registers 
    5170class VR<bits<5> num, string n> : PPCReg<n> { 
    5271  field bits<5> Num = num; 
     
    166185def F30 : FPR<30, "f30">, DwarfRegNum<[62, 62]>; 
    167186def F31 : FPR<31, "f31">, DwarfRegNum<[63, 63]>; 
    168187 
     188// Extended FPR parts (used for FP2 and QPX) 
     189def F0_ext  : FPR_ext<"f0_ext">; 
     190def F1_ext  : FPR_ext<"f1_ext">; 
     191def F2_ext  : FPR_ext<"f2_ext">; 
     192def F3_ext  : FPR_ext<"f3_ext">; 
     193def F4_ext  : FPR_ext<"f4_ext">; 
     194def F5_ext  : FPR_ext<"f5_ext">; 
     195def F6_ext  : FPR_ext<"f6_ext">; 
     196def F7_ext  : FPR_ext<"f7_ext">; 
     197def F8_ext  : FPR_ext<"f8_ext">; 
     198def F9_ext  : FPR_ext<"f9_ext">; 
     199def F10_ext : FPR_ext<"f10_ext">; 
     200def F11_ext : FPR_ext<"f11_ext">; 
     201def F12_ext : FPR_ext<"f12_ext">; 
     202def F13_ext : FPR_ext<"f13_ext">; 
     203def F14_ext : FPR_ext<"f14_ext">; 
     204def F15_ext : FPR_ext<"f15_ext">; 
     205def F16_ext : FPR_ext<"f16_ext">; 
     206def F17_ext : FPR_ext<"f17_ext">; 
     207def F18_ext : FPR_ext<"f18_ext">; 
     208def F19_ext : FPR_ext<"f19_ext">; 
     209def F20_ext : FPR_ext<"f20_ext">; 
     210def F21_ext : FPR_ext<"f21_ext">; 
     211def F22_ext : FPR_ext<"f22_ext">; 
     212def F23_ext : FPR_ext<"f23_ext">; 
     213def F24_ext : FPR_ext<"f24_ext">; 
     214def F25_ext : FPR_ext<"f25_ext">; 
     215def F26_ext : FPR_ext<"f26_ext">; 
     216def F27_ext : FPR_ext<"f27_ext">; 
     217def F28_ext : FPR_ext<"f28_ext">; 
     218def F29_ext : FPR_ext<"f29_ext">; 
     219def F30_ext : FPR_ext<"f30_ext">; 
     220def F31_ext : FPR_ext<"f31_ext">; 
     221 
     222// FP2 (Double Hummer) Floating-point registers 
     223def DF0  : DFPR< F0,  F0_ext,  "df0">, DwarfRegNum<[32, 32]>; 
     224def DF1  : DFPR< F1,  F1_ext,  "df1">, DwarfRegNum<[33, 33]>; 
     225def DF2  : DFPR< F2,  F2_ext,  "df2">, DwarfRegNum<[34, 34]>; 
     226def DF3  : DFPR< F3,  F3_ext,  "df3">, DwarfRegNum<[35, 35]>; 
     227def DF4  : DFPR< F4,  F4_ext,  "df4">, DwarfRegNum<[36, 36]>; 
     228def DF5  : DFPR< F5,  F5_ext,  "df5">, DwarfRegNum<[37, 37]>; 
     229def DF6  : DFPR< F6,  F6_ext,  "df6">, DwarfRegNum<[38, 38]>; 
     230def DF7  : DFPR< F7,  F7_ext,  "df7">, DwarfRegNum<[39, 39]>; 
     231def DF8  : DFPR< F8,  F8_ext,  "df8">, DwarfRegNum<[40, 40]>; 
     232def DF9  : DFPR< F9,  F9_ext,  "df9">, DwarfRegNum<[41, 41]>; 
     233def DF10 : DFPR<F10, F10_ext, "df10">, DwarfRegNum<[42, 42]>; 
     234def DF11 : DFPR<F11, F11_ext, "df11">, DwarfRegNum<[43, 43]>; 
     235def DF12 : DFPR<F12, F12_ext, "df12">, DwarfRegNum<[44, 44]>; 
     236def DF13 : DFPR<F13, F13_ext, "df13">, DwarfRegNum<[45, 45]>; 
     237def DF14 : DFPR<F14, F14_ext, "df14">, DwarfRegNum<[46, 46]>; 
     238def DF15 : DFPR<F15, F15_ext, "df15">, DwarfRegNum<[47, 47]>; 
     239def DF16 : DFPR<F16, F16_ext, "df16">, DwarfRegNum<[48, 48]>; 
     240def DF17 : DFPR<F17, F17_ext, "df17">, DwarfRegNum<[49, 49]>; 
     241def DF18 : DFPR<F18, F18_ext, "df18">, DwarfRegNum<[50, 50]>; 
     242def DF19 : DFPR<F19, F19_ext, "df19">, DwarfRegNum<[51, 51]>; 
     243def DF20 : DFPR<F20, F20_ext, "df20">, DwarfRegNum<[52, 52]>; 
     244def DF21 : DFPR<F21, F21_ext, "df21">, DwarfRegNum<[53, 53]>; 
     245def DF22 : DFPR<F22, F22_ext, "df22">, DwarfRegNum<[54, 54]>; 
     246def DF23 : DFPR<F23, F23_ext, "df23">, DwarfRegNum<[55, 55]>; 
     247def DF24 : DFPR<F24, F24_ext, "df24">, DwarfRegNum<[56, 56]>; 
     248def DF25 : DFPR<F25, F25_ext, "df25">, DwarfRegNum<[57, 57]>; 
     249def DF26 : DFPR<F26, F26_ext, "df26">, DwarfRegNum<[58, 58]>; 
     250def DF27 : DFPR<F27, F27_ext, "df27">, DwarfRegNum<[59, 59]>; 
     251def DF28 : DFPR<F28, F28_ext, "df28">, DwarfRegNum<[60, 60]>; 
     252def DF29 : DFPR<F29, F29_ext, "df29">, DwarfRegNum<[61, 61]>; 
     253def DF30 : DFPR<F30, F30_ext, "df30">, DwarfRegNum<[62, 62]>; 
     254def DF31 : DFPR<F31, F31_ext, "df31">, DwarfRegNum<[63, 63]>; 
     255 
     256// QPX Floating-point registers 
     257def QF0  : QFPR< F0,  F0_ext,  "qf0">, DwarfRegNum<[32, 32]>; 
     258def QF1  : QFPR< F1,  F1_ext,  "qf1">, DwarfRegNum<[33, 33]>; 
     259def QF2  : QFPR< F2,  F2_ext,  "qf2">, DwarfRegNum<[34, 34]>; 
     260def QF3  : QFPR< F3,  F3_ext,  "qf3">, DwarfRegNum<[35, 35]>; 
     261def QF4  : QFPR< F4,  F4_ext,  "qf4">, DwarfRegNum<[36, 36]>; 
     262def QF5  : QFPR< F5,  F5_ext,  "qf5">, DwarfRegNum<[37, 37]>; 
     263def QF6  : QFPR< F6,  F6_ext,  "qf6">, DwarfRegNum<[38, 38]>; 
     264def QF7  : QFPR< F7,  F7_ext,  "qf7">, DwarfRegNum<[39, 39]>; 
     265def QF8  : QFPR< F8,  F8_ext,  "qf8">, DwarfRegNum<[40, 40]>; 
     266def QF9  : QFPR< F9,  F9_ext,  "qf9">, DwarfRegNum<[41, 41]>; 
     267def QF10 : QFPR<F10, F10_ext, "qf10">, DwarfRegNum<[42, 42]>; 
     268def QF11 : QFPR<F11, F11_ext, "qf11">, DwarfRegNum<[43, 43]>; 
     269def QF12 : QFPR<F12, F12_ext, "qf12">, DwarfRegNum<[44, 44]>; 
     270def QF13 : QFPR<F13, F13_ext, "qf13">, DwarfRegNum<[45, 45]>; 
     271def QF14 : QFPR<F14, F14_ext, "qf14">, DwarfRegNum<[46, 46]>; 
     272def QF15 : QFPR<F15, F15_ext, "qf15">, DwarfRegNum<[47, 47]>; 
     273def QF16 : QFPR<F16, F16_ext, "qf16">, DwarfRegNum<[48, 48]>; 
     274def QF17 : QFPR<F17, F17_ext, "qf17">, DwarfRegNum<[49, 49]>; 
     275def QF18 : QFPR<F18, F18_ext, "qf18">, DwarfRegNum<[50, 50]>; 
     276def QF19 : QFPR<F19, F19_ext, "qf19">, DwarfRegNum<[51, 51]>; 
     277def QF20 : QFPR<F20, F20_ext, "qf20">, DwarfRegNum<[52, 52]>; 
     278def QF21 : QFPR<F21, F21_ext, "qf21">, DwarfRegNum<[53, 53]>; 
     279def QF22 : QFPR<F22, F22_ext, "qf22">, DwarfRegNum<[54, 54]>; 
     280def QF23 : QFPR<F23, F23_ext, "qf23">, DwarfRegNum<[55, 55]>; 
     281def QF24 : QFPR<F24, F24_ext, "qf24">, DwarfRegNum<[56, 56]>; 
     282def QF25 : QFPR<F25, F25_ext, "qf25">, DwarfRegNum<[57, 57]>; 
     283def QF26 : QFPR<F26, F26_ext, "qf26">, DwarfRegNum<[58, 58]>; 
     284def QF27 : QFPR<F27, F27_ext, "qf27">, DwarfRegNum<[59, 59]>; 
     285def QF28 : QFPR<F28, F28_ext, "qf28">, DwarfRegNum<[60, 60]>; 
     286def QF29 : QFPR<F29, F29_ext, "qf29">, DwarfRegNum<[61, 61]>; 
     287def QF30 : QFPR<F30, F30_ext, "qf30">, DwarfRegNum<[62, 62]>; 
     288def QF31 : QFPR<F31, F31_ext, "qf31">, DwarfRegNum<[63, 63]>; 
     289 
    169290// Vector registers 
    170291def V0  : VR< 0,  "v0">, DwarfRegNum<[77, 77]>; 
    171292def V1  : VR< 1,  "v1">, DwarfRegNum<[78, 78]>; 
     
    300421                             V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 
    301422                             V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; 
    302423 
     424// For FP2 
     425def DFRC : RegisterClass<"PPC", [v2f64], 64, (add (sequence "DF%u", 0, 13), 
     426                                                (sequence "DF%u", 31, 14))>; 
     427 
     428// For QPX 
     429def QFRC : RegisterClass<"PPC", [v4f64], 256, (add (sequence "QF%u", 0, 13), 
     430                                                (sequence "QF%u", 31, 14))>; 
     431 
    303432def CRBITRC : RegisterClass<"PPC", [i32], 32, 
    304433  (add CR0LT, CR0GT, CR0EQ, CR0UN, 
    305434       CR1LT, CR1GT, CR1EQ, CR1UN, 
  • lib/Target/PowerPC/PPCSubtarget.cpp

    diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
    index f405b47..ecffb2c 100644
    a b  
    7373  , Use64BitRegs(false) 
    7474  , IsPPC64(is64Bit) 
    7575  , HasAltivec(false) 
     76  , HasFP2(false) 
     77  , HasQPX(false) 
    7678  , HasFSQRT(false) 
    7779  , HasSTFIWX(false) 
    7880  , IsBookE(false) 
     
    110112  // Set up darwin-specific properties. 
    111113  if (isDarwin()) 
    112114    HasLazyResolverStubs = true; 
     115 
     116  // QPX requires a 32-byte aligned stack 
     117  if (hasQPX()) 
     118    StackAlignment = 32; 
    113119} 
    114120 
    115121/// SetJITMode - This is called to inform the subtarget info that we are 
  • lib/Target/PowerPC/PPCSubtarget.h

    diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h
    index a275029..9caea71 100644
    a b  
    6666  bool Use64BitRegs; 
    6767  bool IsPPC64; 
    6868  bool HasAltivec; 
     69  bool HasFP2; 
     70  bool HasQPX; 
    6971  bool HasFSQRT; 
    7072  bool HasSTFIWX; 
    7173  bool IsBookE; 
     
    138140  bool hasFSQRT() const { return HasFSQRT; } 
    139141  bool hasSTFIWX() const { return HasSTFIWX; } 
    140142  bool hasAltivec() const { return HasAltivec; } 
     143  bool hasFP2() const { return HasFP2; } 
     144  bool hasQPX() const { return HasQPX; } 
    141145  bool isGigaProcessor() const { return IsGigaProcessor; } 
    142146  bool isBookE() const { return IsBookE; } 
    143147 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-add-int.ll

    diff --git a/lib/Transforms/Vectorize/BBVectorize.exports b/lib/Transforms/Vectorize/BBVectorize.exports
    new file mode 100644
    index 0000000..e69de29
    diff --git a/test/CodeGen/PowerPC/fp2-add-int.ll b/test/CodeGen/PowerPC/fp2-add-int.ll
    new file mode 100644
    index 0000000..5ed28bf
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fpadd(<2 x double>, <2 x double>) 
     4declare <2 x double> @llvm.ppc.fp2.fpsub(<2 x double>, <2 x double>) 
     5 
     6define <2 x double> @test1(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     7entry: 
     8  %c = call <2 x double> @llvm.ppc.fp2.fpadd(<2 x double> %a, <2 x double> %b) 
     9  ret <2 x double> %c 
     10; CHECK: fpadd 
     11} 
     12 
     13define <2 x double> @test2(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     14entry: 
     15  %c = call <2 x double> @llvm.ppc.fp2.fpsub(<2 x double> %a, <2 x double> %b) 
     16  ret <2 x double> %c 
     17; CHECK: fpsub 
     18} 
     19 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-add.ll

    diff --git a/test/CodeGen/PowerPC/fp2-add.ll b/test/CodeGen/PowerPC/fp2-add.ll
    new file mode 100644
    index 0000000..2d10199
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3define <2 x double> @test1(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     4entry: 
     5  %c = fadd <2 x double> %a, %b 
     6  ret <2 x double> %c 
     7; CHECK: fpadd 
     8} 
     9 
     10define <2 x double> @test2(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     11entry: 
     12  %c = fsub <2 x double> %a, %b 
     13  ret <2 x double> %c 
     14; CHECK: fpsub 
     15} 
     16 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-asym-madd-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-asym-madd-int.ll b/test/CodeGen/PowerPC/fp2-asym-madd-int.ll
    new file mode 100644
    index 0000000..f3750fc
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fxcpnpma(<2 x double>, <2 x double>, <2 x double>) 
     4declare <2 x double> @llvm.ppc.fp2.fxcsnpma(<2 x double>, <2 x double>, <2 x double>) 
     5declare <2 x double> @llvm.ppc.fp2.fxcpnsma(<2 x double>, <2 x double>, <2 x double>) 
     6declare <2 x double> @llvm.ppc.fp2.fxcsnsma(<2 x double>, <2 x double>, <2 x double>) 
     7 
     8define <2 x double> @test1(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     9entry: 
     10  %d = call <2 x double> @llvm.ppc.fp2.fxcpnpma(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     11  ret <2 x double> %d 
     12; CHECK: fxcpnpma 
     13} 
     14 
     15define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     16entry: 
     17  %d = call <2 x double> @llvm.ppc.fp2.fxcsnpma(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     18  ret <2 x double> %d 
     19; CHECK: fxcsnpma 
     20} 
     21 
     22define <2 x double> @test3(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     23entry: 
     24  %d = call <2 x double> @llvm.ppc.fp2.fxcpnsma(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     25  ret <2 x double> %d 
     26; CHECK: fxcpnsma 
     27} 
     28 
     29define <2 x double> @test4(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     30entry: 
     31  %d = call <2 x double> @llvm.ppc.fp2.fxcsnsma(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     32  ret <2 x double> %d 
     33; CHECK: fxcsnsma 
     34} 
     35 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-cmplx-madd-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-cmplx-madd-int.ll b/test/CodeGen/PowerPC/fp2-cmplx-madd-int.ll
    new file mode 100644
    index 0000000..de2f0af
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fxcxnpma(<2 x double>, <2 x double>, <2 x double>) 
     4declare <2 x double> @llvm.ppc.fp2.fxcxnsma(<2 x double>, <2 x double>, <2 x double>) 
     5declare <2 x double> @llvm.ppc.fp2.fxcxma(<2 x double>, <2 x double>, <2 x double>) 
     6declare <2 x double> @llvm.ppc.fp2.fxcxnms(<2 x double>, <2 x double>, <2 x double>) 
     7 
     8define <2 x double> @test1(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     9entry: 
     10  %d = call <2 x double> @llvm.ppc.fp2.fxcxnpma(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     11  ret <2 x double> %d 
     12; CHECK: fxcxnpma 
     13} 
     14 
     15define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     16entry: 
     17  %d = call <2 x double> @llvm.ppc.fp2.fxcxnsma(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     18  ret <2 x double> %d 
     19; CHECK: fxcxnsma 
     20} 
     21 
     22define <2 x double> @test3(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     23entry: 
     24  %d = call <2 x double> @llvm.ppc.fp2.fxcxma(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     25  ret <2 x double> %d 
     26; CHECK: fxcxma 
     27} 
     28 
     29define <2 x double> @test4(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     30entry: 
     31  %d = call <2 x double> @llvm.ppc.fp2.fxcxnms(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     32  ret <2 x double> %d 
     33; CHECK: fxcxnms 
     34} 
     35 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-est-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-est-int.ll b/test/CodeGen/PowerPC/fp2-est-int.ll
    new file mode 100644
    index 0000000..f905b33
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fpre(<2 x double>) 
     4declare <2 x double> @llvm.ppc.fp2.fprsqrte(<2 x double>) 
     5 
     6define <2 x double> @test1(<2 x double> %a) nounwind readnone { 
     7entry: 
     8  %c = call <2 x double> @llvm.ppc.fp2.fpre(<2 x double> %a) 
     9  ret <2 x double> %c 
     10; CHECK: fpre 
     11} 
     12 
     13define <2 x double> @test2(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     14entry: 
     15  %c = call <2 x double> @llvm.ppc.fp2.fprsqrte(<2 x double> %a) 
     16  ret <2 x double> %c 
     17; CHECK: fprsqrte 
     18} 
     19 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-fsel-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-fsel-int.ll b/test/CodeGen/PowerPC/fp2-fsel-int.ll
    new file mode 100644
    index 0000000..7178666
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fpsel(<2 x double>, <2 x double>, <2 x double>) 
     4 
     5define <2 x double> @test1(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     6entry: 
     7  %d = call <2 x double> @llvm.ppc.fp2.fpsel(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     8  ret <2 x double> %d 
     9; CHECK: fpsel 
     10} 
     11 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-ld-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-ld-int.ll b/test/CodeGen/PowerPC/fp2-ld-int.ll
    new file mode 100644
    index 0000000..5a254e7
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.lfpd(double*) 
     4declare <2 x double> @llvm.ppc.fp2.lfps(float*) 
     5declare <2 x double> @llvm.ppc.fp2.lfxd(double*) 
     6declare <2 x double> @llvm.ppc.fp2.lfxs(float*) 
     7 
     8define <2 x double> @test1(double* %a) nounwind readnone { 
     9entry: 
     10  %b = call <2 x double> @llvm.ppc.fp2.lfpd(double* %a) 
     11  ret <2 x double> %b 
     12; CHECK: lfpdx 
     13} 
     14 
     15define <2 x double> @test2(float* %a) nounwind readnone { 
     16entry: 
     17  %b = call <2 x double> @llvm.ppc.fp2.lfps(float* %a) 
     18  ret <2 x double> %b 
     19; CHECK: lfpsx 
     20} 
     21 
     22define <2 x double> @test3(double* %a) nounwind readnone { 
     23entry: 
     24  %b = call <2 x double> @llvm.ppc.fp2.lfxd(double* %a) 
     25  ret <2 x double> %b 
     26; CHECK: lfxdx 
     27} 
     28 
     29define <2 x double> @test4(float* %a) nounwind readnone { 
     30entry: 
     31  %b = call <2 x double> @llvm.ppc.fp2.lfxs(float* %a) 
     32  ret <2 x double> %b 
     33; CHECK: lfxsx 
     34} 
     35 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-madd-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-madd-int.ll b/test/CodeGen/PowerPC/fp2-madd-int.ll
    new file mode 100644
    index 0000000..b5ab3ad
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fpmadd(<2 x double>, <2 x double>, <2 x double>) 
     4declare <2 x double> @llvm.ppc.fp2.fpnmadd(<2 x double>, <2 x double>, <2 x double>) 
     5declare <2 x double> @llvm.ppc.fp2.fpmsub(<2 x double>, <2 x double>, <2 x double>) 
     6declare <2 x double> @llvm.ppc.fp2.fpnmsub(<2 x double>, <2 x double>, <2 x double>) 
     7declare <2 x double> @llvm.ppc.fp2.fxmadd(<2 x double>, <2 x double>, <2 x double>) 
     8declare <2 x double> @llvm.ppc.fp2.fxnmadd(<2 x double>, <2 x double>, <2 x double>) 
     9declare <2 x double> @llvm.ppc.fp2.fxmsub(<2 x double>, <2 x double>, <2 x double>) 
     10declare <2 x double> @llvm.ppc.fp2.fxnmsub(<2 x double>, <2 x double>, <2 x double>) 
     11declare <2 x double> @llvm.ppc.fp2.fxcpmadd(<2 x double>, <2 x double>, <2 x double>) 
     12declare <2 x double> @llvm.ppc.fp2.fxcsmadd(<2 x double>, <2 x double>, <2 x double>) 
     13declare <2 x double> @llvm.ppc.fp2.fxcpnmadd(<2 x double>, <2 x double>, <2 x double>) 
     14declare <2 x double> @llvm.ppc.fp2.fxcsnmadd(<2 x double>, <2 x double>, <2 x double>) 
     15declare <2 x double> @llvm.ppc.fp2.fxcpmsub(<2 x double>, <2 x double>, <2 x double>) 
     16declare <2 x double> @llvm.ppc.fp2.fxcsmsub(<2 x double>, <2 x double>, <2 x double>) 
     17declare <2 x double> @llvm.ppc.fp2.fxcpnmsub(<2 x double>, <2 x double>, <2 x double>) 
     18declare <2 x double> @llvm.ppc.fp2.fxcsnmsub(<2 x double>, <2 x double>, <2 x double>) 
     19 
     20define <2 x double> @test1(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     21entry: 
     22  %d = call <2 x double> @llvm.ppc.fp2.fpmadd(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     23  ret <2 x double> %d 
     24; CHECK: fpmadd 
     25} 
     26 
     27define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     28entry: 
     29  %d = call <2 x double> @llvm.ppc.fp2.fpnmadd(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     30  ret <2 x double> %d 
     31; CHECK: fpnmadd 
     32} 
     33 
     34define <2 x double> @test3(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     35entry: 
     36  %d = call <2 x double> @llvm.ppc.fp2.fpmsub(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     37  ret <2 x double> %d 
     38; CHECK: fpmsub 
     39} 
     40 
     41define <2 x double> @test4(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     42entry: 
     43  %d = call <2 x double> @llvm.ppc.fp2.fpnmsub(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     44  ret <2 x double> %d 
     45; CHECK: fpnmsub 
     46} 
     47 
     48define <2 x double> @test5(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     49entry: 
     50  %d = call <2 x double> @llvm.ppc.fp2.fxmadd(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     51  ret <2 x double> %d 
     52; CHECK: fxmadd 
     53} 
     54 
     55define <2 x double> @test6(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     56entry: 
     57  %d = call <2 x double> @llvm.ppc.fp2.fxnmadd(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     58  ret <2 x double> %d 
     59; CHECK: fxnmadd 
     60} 
     61 
     62define <2 x double> @test7(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     63entry: 
     64  %d = call <2 x double> @llvm.ppc.fp2.fxmsub(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     65  ret <2 x double> %d 
     66; CHECK: fxmsub 
     67} 
     68 
     69define <2 x double> @test8(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     70entry: 
     71  %d = call <2 x double> @llvm.ppc.fp2.fxnmsub(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     72  ret <2 x double> %d 
     73; CHECK: fxnmsub 
     74} 
     75 
     76define <2 x double> @test9(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     77entry: 
     78  %d = call <2 x double> @llvm.ppc.fp2.fxcpmadd(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     79  ret <2 x double> %d 
     80; CHECK: fxcpmadd 
     81} 
     82 
     83define <2 x double> @test10(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     84entry: 
     85  %d = call <2 x double> @llvm.ppc.fp2.fxcsmadd(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     86  ret <2 x double> %d 
     87; CHECK: fxcsmadd 
     88} 
     89 
     90define <2 x double> @test11(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     91entry: 
     92  %d = call <2 x double> @llvm.ppc.fp2.fxcpnmadd(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     93  ret <2 x double> %d 
     94; CHECK: fxcpnmadd 
     95} 
     96 
     97define <2 x double> @test12(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     98entry: 
     99  %d = call <2 x double> @llvm.ppc.fp2.fxcsnmadd(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     100  ret <2 x double> %d 
     101; CHECK: fxcsnmadd 
     102} 
     103 
     104define <2 x double> @test13(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     105entry: 
     106  %d = call <2 x double> @llvm.ppc.fp2.fxcpmsub(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     107  ret <2 x double> %d 
     108; CHECK: fxcpmsub 
     109} 
     110 
     111define <2 x double> @test14(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     112entry: 
     113  %d = call <2 x double> @llvm.ppc.fp2.fxcsmsub(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     114  ret <2 x double> %d 
     115; CHECK: fxcsmsub 
     116} 
     117 
     118define <2 x double> @test15(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     119entry: 
     120  %d = call <2 x double> @llvm.ppc.fp2.fxcpnmsub(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     121  ret <2 x double> %d 
     122; CHECK: fxcpnmsub 
     123} 
     124 
     125define <2 x double> @test16(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone { 
     126entry: 
     127  %d = call <2 x double> @llvm.ppc.fp2.fxcsnmsub(<2 x double> %a, <2 x double> %b, <2 x double> %c) 
     128  ret <2 x double> %d 
     129; CHECK: fxcsnmsub 
     130} 
     131 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-mul-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-mul-int.ll b/test/CodeGen/PowerPC/fp2-mul-int.ll
    new file mode 100644
    index 0000000..c272d61
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fpmul(<2 x double>, <2 x double>) 
     4declare <2 x double> @llvm.ppc.fp2.fxmul(<2 x double>, <2 x double>) 
     5declare <2 x double> @llvm.ppc.fp2.fxpmul(<2 x double>, <2 x double>) 
     6declare <2 x double> @llvm.ppc.fp2.fxsmul(<2 x double>, <2 x double>) 
     7 
     8define <2 x double> @test1(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     9entry: 
     10  %c = call <2 x double> @llvm.ppc.fp2.fpmul(<2 x double> %a, <2 x double> %b) 
     11  ret <2 x double> %c 
     12; CHECK: fpmul 
     13} 
     14 
     15define <2 x double> @test2(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     16entry: 
     17  %c = call <2 x double> @llvm.ppc.fp2.fxmul(<2 x double> %a, <2 x double> %b) 
     18  ret <2 x double> %c 
     19; CHECK: fxmul 
     20} 
     21 
     22define <2 x double> @test3(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     23entry: 
     24  %c = call <2 x double> @llvm.ppc.fp2.fxpmul(<2 x double> %a, <2 x double> %b) 
     25  ret <2 x double> %c 
     26; CHECK: fxpmul 
     27} 
     28 
     29define <2 x double> @test4(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     30entry: 
     31  %c = call <2 x double> @llvm.ppc.fp2.fxsmul(<2 x double> %a, <2 x double> %b) 
     32  ret <2 x double> %c 
     33; CHECK: fxsmul 
     34} 
     35 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-mul.ll

    diff --git a/test/CodeGen/PowerPC/fp2-mul.ll b/test/CodeGen/PowerPC/fp2-mul.ll
    new file mode 100644
    index 0000000..a8e05ae
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3define <2 x double> @test1(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     4entry: 
     5  %c = fmul <2 x double> %a, %b 
     6  ret <2 x double> %c 
     7; CHECK: fpmul 
     8} 
     9 
     10define <2 x double> @test2(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     11entry: 
     12  %c = shufflevector < 2 x double> %b, <2 x double> undef, <2 x i32> <i32 1, i32 0> 
     13  %d = fmul <2 x double> %a, %c 
     14  ret <2 x double> %d 
     15; CHECK: fxmul 
     16} 
     17 
     18define <2 x double> @test3(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     19entry: 
     20  %c = shufflevector < 2 x double> %a, <2 x double> undef, <2 x i32> <i32 0, i32 0> 
     21  %d = fmul <2 x double> %b, %c 
     22  ret <2 x double> %d 
     23; CHECK: fxpmul 
     24} 
     25 
     26define <2 x double> @test4(<2 x double> %a, <2 x double> %b) nounwind readnone { 
     27entry: 
     28  %c = shufflevector < 2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 1> 
     29  %d = fmul <2 x double> %b, %c 
     30  ret <2 x double> %d 
     31; CHECK: fxsmul 
     32} 
     33 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-mv-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-mv-int.ll b/test/CodeGen/PowerPC/fp2-mv-int.ll
    new file mode 100644
    index 0000000..5df894c
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fpneg(<2 x double>) 
     4declare <2 x double> @llvm.ppc.fp2.fpabs(<2 x double>) 
     5declare <2 x double> @llvm.ppc.fp2.fpnabs(<2 x double>) 
     6declare <2 x double> @llvm.ppc.fp2.fxmr(<2 x double>) 
     7 
     8define <2 x double> @test1(<2 x double> %a) nounwind readnone { 
     9entry: 
     10  %b = call <2 x double> @llvm.ppc.fp2.fpneg(<2 x double> %a) 
     11  ret <2 x double> %b 
     12; CHECK: fpneg 
     13} 
     14 
     15define <2 x double> @test2(<2 x double> %a) nounwind readnone { 
     16entry: 
     17  %b = call <2 x double> @llvm.ppc.fp2.fpabs(<2 x double> %a) 
     18  ret <2 x double> %b 
     19; CHECK: fpabs 
     20} 
     21 
     22define <2 x double> @test3(<2 x double> %a) nounwind readnone { 
     23entry: 
     24  %b = call <2 x double> @llvm.ppc.fp2.fpnabs(<2 x double> %a) 
     25  ret <2 x double> %b 
     26; CHECK: fpnabs 
     27} 
     28 
     29define <2 x double> @test4(<2 x double> %a) nounwind readnone { 
     30entry: 
     31  %b = call <2 x double> @llvm.ppc.fp2.fxmr(<2 x double> %a) 
     32  ret <2 x double> %b 
     33; CHECK: fxmr 
     34} 
     35 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-rnd-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-rnd-int.ll b/test/CodeGen/PowerPC/fp2-rnd-int.ll
    new file mode 100644
    index 0000000..6ac6ead
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare <2 x double> @llvm.ppc.fp2.fpctiw(<2 x double>) 
     4declare <2 x double> @llvm.ppc.fp2.fpctiwz(<2 x double>) 
     5declare <2 x double> @llvm.ppc.fp2.fprsp(<2 x double>) 
     6 
     7define <2 x double> @test1(<2 x double> %a) nounwind readnone { 
     8entry: 
     9  %b = call <2 x double> @llvm.ppc.fp2.fpctiw(<2 x double> %a) 
     10  ret <2 x double> %b 
     11; CHECK: fpctiw 
     12} 
     13 
     14define <2 x double> @test2(<2 x double> %a) nounwind readnone { 
     15entry: 
     16  %b = call <2 x double> @llvm.ppc.fp2.fpctiwz(<2 x double> %a) 
     17  ret <2 x double> %b 
     18; CHECK: fpctiwz 
     19} 
     20 
     21define <2 x double> @test3(<2 x double> %a) nounwind readnone { 
     22entry: 
     23  %b = call <2 x double> @llvm.ppc.fp2.fprsp(<2 x double> %a) 
     24  ret <2 x double> %b 
     25; CHECK: fprsp 
     26} 
     27 
  • (a) /dev/null vs. (b) b/test/CodeGen/PowerPC/fp2-st-int.ll

    diff --git a/test/CodeGen/PowerPC/fp2-st-int.ll b/test/CodeGen/PowerPC/fp2-st-int.ll
    new file mode 100644
    index 0000000..ba4bda0
    a b  
     1; RUN: llc < %s -march=ppc32 -mcpu=440fp2 | FileCheck %s 
     2 
     3declare void @llvm.ppc.fp2.stfpd(<2 x double>, double*) 
     4declare void @llvm.ppc.fp2.stfps(<2 x double>, float*) 
     5declare void @llvm.ppc.fp2.stfxd(<2 x double>, double*) 
     6declare void @llvm.ppc.fp2.stfxs(<2 x double>, float*) 
     7declare void @llvm.ppc.fp2.stfpiw(<2 x double>, i32*) 
     8 
     9define void @test1(<2 x double> %a, double* %b) nounwind readnone { 
     10entry: 
     11  call void @llvm.ppc.fp2.stfpd(<2 x double> %a, double* %b) 
     12  ret void 
     13; CHECK: stfpdx 
     14} 
     15 
     16define void @test2(<2 x double> %a, float* %b) nounwind readnone { 
     17entry: 
     18  call void @llvm.ppc.fp2.stfps(<2 x double> %a, float* %b) 
     19  ret void 
     20; CHECK: stfpsx 
     21} 
     22 
     23define void @test3(<2 x double> %a, double* %b) nounwind readnone { 
     24entry: 
     25  call void @llvm.ppc.fp2.stfxd(<2 x double> %a, double* %b) 
     26  ret void 
     27; CHECK: stfxdx 
     28} 
     29 
     30define void @test4(<2 x double> %a, float* %b) nounwind readnone { 
     31entry: 
     32  call void @llvm.ppc.fp2.stfxs(<2 x double> %a, float* %b) 
     33  ret void 
     34; CHECK: stfxsx 
     35} 
     36 
     37define void @test5(<2 x double> %a, i32* %b) nounwind readnone { 
     38entry: 
     39  call void @llvm.ppc.fp2.stfpiw(<2 x double> %a, i32* %b) 
     40  ret void 
     41; CHECK: stfpiwx 
     42} 
     43 
  • test/CodeGen/PowerPC/vec_buildvector_loadstore.ll

    diff --git a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
    index 015c086..b4dc481 100644
    a b  
    66 
    77define void @foo() nounwind ssp { 
    88; CHECK: _foo: 
     9; CHECK: mtspr 
    910; CHECK-NOT: stw 
    1011entry: 
    1112    %tmp0 = load <16 x i8>* @a, align 16 
  • test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll

    diff --git a/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll b/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll
    index da02907..0c181ff 100644
    a b  
    22; PR2082 
    33; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of 
    44; registers. 
     5 
     6; store reordering causes this to run out of registers anyway... 
     7; XFAIL: * 
     8 
    59define void @transpose4x4(i8* %dst, i8* %src, i32 %dst_stride, i32 %src_stride) { 
    610entry: 
    711        %dst_addr = alloca i8*          ; <i8**> [#uses=5] 
  • test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll

    diff --git a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
    index 1b33977..10e5ea5 100644
    a b  
    1818  ret i32 0 
    1919} 
    2020 
     21; store reordering has changed this... 
     22; XFAIL: * 
     23 
    2124; CHECK: movq   ___stack_chk_guard@GOTPCREL(%rip) 
    22 ; CHECK: movb   38(%rsp), [[R0:%.+]] 
    2325; CHECK: movb   8(%rsp), [[R1:%.+]] 
    24 ; CHECK: movb   [[R1]], 8(%rsp) 
     26; CHECK: movb   38(%rsp), [[R0:%.+]] 
    2527; CHECK: movb   [[R0]], 38(%rsp) 
     28; CHECK: movb   [[R1]], 8(%rsp) 
    2629; CHECK: callq  ___stack_chk_fail 
  • test/CodeGen/X86/ghc-cc64.ll

    diff --git a/test/CodeGen/X86/ghc-cc64.ll b/test/CodeGen/X86/ghc-cc64.ll
    index fcf7e17..a56b84d 100644
    a b  
    4141 
    4242define cc 10 void @foo() nounwind { 
    4343entry: 
    44   ; CHECK: movq base(%rip), %r13 
     44  ; CHECK: movsd d2(%rip), %xmm6 
     45  ; CHECK-NEXT: movsd d1(%rip), %xmm5 
     46  ; CHECK-NEXT: movss f4(%rip), %xmm4 
     47  ; CHECK-NEXT: movss f3(%rip), %xmm3 
     48  ; CHECK-NEXT: movss f2(%rip), %xmm2 
     49  ; CHECK-NEXT: movss f1(%rip), %xmm1 
     50  ; CHECK-NEXT: movq splim(%rip), %r15 
     51  ; CHECK-NEXT: movq r5(%rip), %r8 
     52  ; CHECK-NEXT: movq r6(%rip), %r9 
     53  ; CHECK-NEXT: movq base(%rip), %r13 
    4554  ; CHECK-NEXT: movq sp(%rip), %rbp 
    4655  ; CHECK-NEXT: movq hp(%rip), %r12 
    4756  ; CHECK-NEXT: movq r1(%rip), %rbx 
    4857  ; CHECK-NEXT: movq r2(%rip), %r14 
    4958  ; CHECK-NEXT: movq r3(%rip), %rsi 
    5059  ; CHECK-NEXT: movq r4(%rip), %rdi 
    51   ; CHECK-NEXT: movq r5(%rip), %r8 
    52   ; CHECK-NEXT: movq r6(%rip), %r9 
    53   ; CHECK-NEXT: movq splim(%rip), %r15 
    54   ; CHECK-NEXT: movss f1(%rip), %xmm1 
    55   ; CHECK-NEXT: movss f2(%rip), %xmm2 
    56   ; CHECK-NEXT: movss f3(%rip), %xmm3 
    57   ; CHECK-NEXT: movss f4(%rip), %xmm4 
    58   ; CHECK-NEXT: movsd d1(%rip), %xmm5 
    59   ; CHECK-NEXT: movsd d2(%rip), %xmm6 
    6060  %0 = load double* @d2 
    6161  %1 = load double* @d1 
    6262  %2 = load float* @f4 
  • test/CodeGen/X86/lea-recursion.ll

    diff --git a/test/CodeGen/X86/lea-recursion.ll b/test/CodeGen/X86/lea-recursion.ll
    index 3f32fd2..89266d2 100644
    a b  
    11; RUN: llc < %s -march=x86-64 | grep lea | count 12 
    22 
     3; store reordering has changed this count to 13, is that okay? 
     4; XFAIL: * 
     5 
    36; This testcase was written to demonstrate an instruction-selection problem, 
    47; however it also happens to expose a limitation in the DAGCombiner's 
    58; expression reassociation which causes it to miss opportunities for 
  • test/CodeGen/X86/narrow-shl-load.ll

    diff --git a/test/CodeGen/X86/narrow-shl-load.ll b/test/CodeGen/X86/narrow-shl-load.ll
    index 7822453..f375821 100644
    a b  
    3434; DAGCombiner shouldn't fold the sdiv (ashr) away. 
    3535; rdar://8636812 
    3636; CHECK: test2: 
    37 ; CHECK:   sarl 
     37 
     38; This check has been disabled b/c with store reordering the sdiv 
     39; is combined away. 
     40; CHECK XX:   sarl 
    3841 
    3942define i32 @test2() nounwind { 
    4043entry: 
  • test/CodeGen/X86/nontemporal.ll

    diff --git a/test/CodeGen/X86/nontemporal.ll b/test/CodeGen/X86/nontemporal.ll
    index ae04435..263d715 100644
    a b  
    11; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s 
    22 
    33define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E) { 
     4; CHECK: movnti 
    45; CHECK: movntps 
     6; CHECK: movntdq 
     7; CHECK: movntpd 
    58  %cast = bitcast i8* %B to <4 x float>* 
    69  %A2 = fadd <4 x float> %A, <float 0x0, float 0x0, float 0x0, float 0x4200000000000000> 
    710  store <4 x float> %A2, <4 x float>* %cast, align 16, !nontemporal !0 
    8 ; CHECK: movntdq 
    911  %cast1 = bitcast i8* %B to <2 x i64>* 
    1012  %E2 = add <2 x i64> %E, <i64 1, i64 2> 
    1113  store <2 x i64> %E2, <2 x i64>* %cast1, align 16, !nontemporal !0 
    12 ; CHECK: movntpd 
    1314  %cast2 = bitcast i8* %B to <2 x double>* 
    1415  %C2 = fadd <2 x double> %C, <double 0x0, double 0x4200000000000000> 
    1516  store <2 x double> %C2, <2 x double>* %cast2, align 16, !nontemporal !0 
    16 ; CHECK: movnti 
    1717  %cast3 = bitcast i8* %B to i32* 
    1818  store i32 %D, i32* %cast3, align 16, !nontemporal !0 
    1919  ret void 
  • test/CodeGen/X86/peep-test-3.ll

    diff --git a/test/CodeGen/X86/peep-test-3.ll b/test/CodeGen/X86/peep-test-3.ll
    index a379980..3764088 100644
    a b  
    4949  %1 = and i32 %0, 3                              ; <i32> [#uses=1] 
    5050  %2 = xor i32 %IA, 1                             ; <i32> [#uses=1] 
    5151; CHECK:      andl  $3, % 
    52 ; CHECK-NEXT: movb  % 
    53 ; CHECK-NEXT: je 
     52; CHECK: movb  % 
     53; CHECK: je 
    5454  %3 = and i32 %2, %1                              ; <i32> [#uses=1] 
    5555  %t = trunc i32 %3 to i8 
    5656  store i8 %t, i8* %p 
  • test/CodeGen/X86/store-narrow.ll

    diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll
    index 0dd228e..316cd4a 100644
    a b  
    130130@g_16 = internal global i32 -1 
    131131 
    132132; X64: test8: 
    133 ; X64-NEXT: movl _g_16(%rip), %eax 
     133; X64-NEXT: movb _g_16(%rip), %al 
     134; X64-NEXT: orb  $1, %al 
     135; X64-NEXT: movb %al, _g_16(%rip) 
    134136; X64-NEXT: movl $0, _g_16(%rip) 
    135 ; X64-NEXT: orl  $1, %eax 
    136 ; X64-NEXT: movl %eax, _g_16(%rip) 
    137137; X64-NEXT: ret 
    138138define void @test8() nounwind { 
    139139  %tmp = load i32* @g_16 
  • (a) /dev/null vs. (b) b/test/Transforms/BBVectorize/dg.exp

    diff --git a/test/Transforms/BBVectorize/dg.exp b/test/Transforms/BBVectorize/dg.exp
    new file mode 100644
    index 0000000..f200589
    a b  
     1load_lib llvm.exp 
     2 
     3RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]